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특허 상세정보

Electronic circuit assembly an a substrate containing programmable switches

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H02J-003/14   
미국특허분류(USC) 307/38 ; 340/825
출원번호 US-0136244 (1993-10-15)
우선권정보 GB-0022840 (1992-10-31)
발명자 / 주소
출원인 / 주소
인용정보 피인용 횟수 : 51  인용 특허 : 0
초록

An electronic assembly has a substrate with several conductive tracks and with a switching matrix within the thickness of the substrate. Several groups of identical integrated circuits are mounted on the substrate, one circuit from each group being operatively connected into the assembly by the switching matrix. A processor detects malfunction of a circuit and controls the switching matrix to disconnect that circuit and operatively connect into the assembly an alternative circuit from the same group.

대표
청구항

An electronic assembly comprising: a substrate, said substrate having a plurality of conductive tracks; a plurality of electronic circuit devices; means mounting the electronic devices on the substrate in electrical connection therewith; a memory storing information as to which devices are operatively connected into the assembly; and a plurality of reprogrammable switches within the substrate by which connection of said devices with the tracks can be changed.

이 특허를 인용한 특허 피인용횟수: 51

  1. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2013028380884.
  2. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2015049015352.
  3. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2014048706916.
  4. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2009107606943.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2015109164952.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543795.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098533431.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
  10. Master, Paul L.; Uvacek, Bohumir. Apparatus and method for adaptive multimedia reception and transmission in communication environments. USP2015049002998.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2016059330058.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2014118880849.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2012088250339.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements. USP2017039594723.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2013048412915.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2012078225073.
  17. Howard, Ric; Katragadda, Ramana V.. Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture. USP2009087577799.
  18. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James. Communications module, device, and method for implementing a system acquisition function. USP2009117620097.
  19. Master, Paul L.; Watson, John. Configurable hardware based digital imaging apparatus. USP2009107609297.
  20. Scheuermann, W. James; Hogenauer, Eugene B.. Control node for multi-core system. USP20190110185502.
  21. Furtek, Frederick Curtis; Master, Paul L.. External memory controller. USP2012098266388.
  22. Furtek, Frederick Curtis; Master, Paul L.. External memory controller node. USP2014078769214.
  23. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077984247.
  24. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077979646.
  25. Scheuermann,Walter James. Hardware implementation of the secure hash standard. USP2009027489779.
  26. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2017059665397.
  27. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2012068200799.
  28. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2010017653710.
  29. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2014078782196.
  30. Master,Paul L.; Hogenauer,Eugene; Scheuermann,Walter James. Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements. USP2008017325123.
  31. Heidari-Bateni, Ghobad; Sambhwani, Sharad D.. Internal synchronization control for adaptive integrated circuitry. USP2012108296764.
  32. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2013058442096.
  33. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2010027668229.
  34. Sambhwani,Sharad; Heidari,Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2009037512173.
  35. Master, Paul L.. Method and system for achieving individualized protected space in an operating system. USP2010027660984.
  36. Master, Paul L.. Method and system for creating and programming an adaptive computing engine. USP2011017865847.
  37. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2015059037834.
  38. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2016079396161.
  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2013118589660.
  40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2010077752419.
  41. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2014078767804.
  42. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2012088249135.
  43. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107809050.
  44. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107822109.
  45. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn. Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information. USP2009017478031.
  46. Master, Paul L.. Profiling of software and circuit designs utilizing data operation analyses. USP2012098276135.
  47. Inoue, Kazuki; Oikawa, Kohei; Miyamoto, Yukimasa; Hatsuda, Kosuke; Nomura, Shuou; Suzuki, Kojiro. Semiconductor apparatus, routing module, and control method of semiconductor apparatus. USP2018029900011.
  48. Master,Paul L.; Watson,John. Storage and delivery of device features. USP2009027493375.
  49. Master, Paul L.; Watson, John. System for adapting device standards after manufacture. USP2009107602740.
  50. Master, Paul L.; Watson, John. System for authorizing functionality in adaptable hardware devices. USP201109E042743.
  51. Katragadda, Ramana; Spoltore, Paul; Howard, Ric. Task definition for specifying resource requirements. USP2012018108656.