이 특허를 인용한 특허 (62)

1. Hickert George, Barrier layer to protect a ferroelectric capacitor after contact has been made to the capacitor electrode.

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2. Lucovsky, Gerald, Binary non-crystalline oxide analogs of silicon dioxide for use in gate dielectrics.

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3. Maejima Yukihiko,JPX, Capacitor and method of manufacturing the same.

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4. Hisayoshi Yamoto JP; Akihiko Ochiai JP, Capacitor having ferroelectric film and multiple layers of insulating and protective films for nonvolatile memory cell.

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5. Evans Thomas A. ; Argos ; Jr. George, Completely encapsulated top electrode of a ferroelectric capacitor.

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6. Eastep Brian Lee ; Evans Thomas A., Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced encapsulation layer.

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7. Eastep Brian Lee ; Evans Thomas A., Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced escapsulation layer.

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8. Zambrano, Raffaele, Contact structure for a ferroelectric memory device.

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9. Zambrano, Raffaele; Artoni, Cesare; Corvasce, Chiara, Contact structure for an integrated semiconductor device.

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10. Zambrano,Raffaele; Artoni,Cesare; Corvasce,Chiara, Contact structure for an integrated semiconductor device.

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11. Zambrano, Raffaele, Contact structure for semiconductor devices and corresponding manufacturing process.

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12. Zambrano, Raffaele, Contact structure for semiconductor devices and corresponding manufacturing process.

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13. Kirlin Peter S. ; Summerfelt Scott R. ; McIntryre Paul, Diffusion barriers between noble metal electrodes and metallization layers, and integrated circuit and semiconductor devices comprising same.

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14. Gu, Zongquan; Islam, Mohammad Anwarul; Spanier, Jonathan Eli, Engineered ferroelectric gate devices.

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15. Joseph D. Cuchiaro ; Carlos A. Paz de Araujo ; Larry D. McMillan, Ferroelectric integrated circuit having hydrogen barrier layer.

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16. Cuchiaro Joseph D. ; Furuya Akira,JPX ; Paz de Araujo Carlos A. ; Miyasaka Yoichi,JPX, Ferroelectric integrated circuit having low sensitivity to hydrogen exposure and method for fabricating same.

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17. Cuchiaro, Joseph D.; Furuya, Akira; Paz de Araujo, Carlos A.; Miyasaka, Yoichi, Ferroelectric integrated circuit having low sensitivity to hydrogen exposure and method for fabricating same.

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18. Cuchiaro Joseph D. ; Furuya Akira,JPX ; Paz de Araujo Carlos A. ; Miyasaka Yoichi,JPX, Ferroelectric integrated circuit with protective layer incorporating oxygen and method for fabricating same.

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19. Jung Dong-Jin,KRX ; Kim Ki-Nam,KRX, Ferroelectric memory device.

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20. Natori, Eiji; Kijima, Takeshi, Ferroelectric memory device and method of manufacturing the same.

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21. Jung, Dong-Jin; Kim, Ki-Nam, Ferroelectric memory device having improved ferroelectric characteristics.

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22. Ogata, Kiyoshi; Horikoshi, Kazuhiko; Suenaga, Kazufumi; Kato, Hisayuki; Yoshizumi, Keiichi; Yamazaki, Masahito, Ferroelectric memory device including an upper protection electrode.

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23. Evans Thomas A., Ferroelectric memory device structure useful for preventing hydrogen line degradation.

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24. Thomas A. Evans, Ferroelectric memory device structure useful for preventing hydrogen line degradation.

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25. Jung Dong-jin,KRX, Ferroelectric memory devices including capacitors located outside the active area and made with diffusion barrier layers.

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26. Mi-hyang Lee KR; Dong-jin Jung KR, Ferroelectric memory devices including patterned conductive layers.

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27. Bailey, Richard A., HYDROGEN BARRIER ENCAPSULATION TECHNIQUES FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN CONJUNCTION WITH MULTILEVEL METAL PROCESSING FOR NON-VOLATILE INTEGRATED CIRCU.

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28. Bailey Richard A., Hydrogen barrier encapsulation techniques for the control of hydrogen induced degradation of ferroelectric capacitors in conjunction with multilevel metal processing for non-volatile integrated circu.

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29. Amiotti, Marco; Jung, Jae Hak; Boffito, Claudio, Integrated capacitive device with hydrogen degradable dielectric layer protected by getter layer.

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30. Cuchiaro, Joseph D.; Furuya, Akira; Paz de Araujo, Carlos A.; Miyasaka, Yoichi, Integrated circuit having self-aligned hydrogen barrier layer and method for fabricating same.

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31. Whitaker, Mark R.; Marentette, Leslie Joseph, Interrupt generation and acknowledgment for RFID.

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32. Whitaker, Mark R., Low power, low pin count interface for an RFID transponder.

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33. Bryan C. Hendrix, Low temperature process for high density thin film integrated capacitors and amorphously frustrated ferroelectric materials therefor.

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34. Cuchiaro Joseph D. ; Furuya Akira,JPX ; Paz de Araujo Carlos A. ; Miyasaka Yoichi,JPX, Method for fabricating ferroelectric integrated circuits.

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35. Ooms William J. ; Marshall Daniel S. ; Hallmark Jerald A., Method for making a ferroelectric semiconductor device and a layered structure.

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36. Cuchiaro Joseph D. ; Furuya Akira,JPX ; Paz de Araujo Carlos A. ; Miyasaka Yoichi,JPX, Method of fabricating ferroelectric integrated circuit using dry and wet etching.

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37. Cuchiaro Joseph D. ; Furuya Akira,JPX ; Paz de Araujo Carlos A. ; Miyasaka Yoichi,JPX, Method of fabricating ferroelectric integrated circuit using oxygen to inhibit and repair hydrogen degradation.

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38. Evans Thomas A. ; Argos ; Jr. George, Method of fabricating partially or completely encapsulated top electrode of a ferroelectric capacitor.

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39. Zambrano, Raffaele, Method of forming a contact structure and a ferroelectric memory device.

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40. Yukihiko Maejima JP, Method of manufacturing a ferroelectric capacitor.

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41. Hikosaka, Yukinobu; Ozaki, Yasutaka; Takai, Kazuaki, Method of manufacturing a semiconductor device with a hydrogen barrier layer.

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42. Evans Thomas A., Method of manufacturing ferroelectric memory device useful for preventing hydrogen line degradation.

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43. Kato, Yoshikazu; Tani, Koji; Hashimoto, Takanori, Method of manufacturing semiconductor device having ferro-dielectric material film.

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44. Seh,Huankiat; Min,Yongki, Method of providing a pre-patterned high-k dielectric film.

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45. Kang Chang-seok,KRX, Methods of fabricating integrated circuit ferroelectric memory devices including a material layer on the upper electrodes of the ferroelectric capacitors thereof.

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46. Lucovsky, Gerald, Methods of forming binary noncrystalline oxide analogs of silicon dioxide.

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47. Gabric,Zvonimir; Hartner,Walter; Kr철nke,Matthias; Schindler,G체nther, Microelectronic structure having a hydrogen barrier layer.

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48. Onishi Shigeo (Nara JPX) Ishihara Kazuya (Kyoto JPX), Non-volatile random access memory and fabrication method thereof.

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49. Evans Thomas A. ; Argos ; Jr. George, Partially or completely encapsulated top electrode of a ferroelectric capacitor.

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50. Evans Thomas A. ; Argos ; Jr. George, Partially or completely encapsulated top electrode of a ferroelectric capacitor.

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51. Zambrano, Raffaele, Process for selectively sealing ferroelectric capacitive elements incorporated in semiconductor integrated non-volatile memory cells.

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52. Whitaker, Mark R.; Greefkes, Kirk, RFID interface and interrupt.

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53. Peng Chien-Hsiung (Blacksburg VA) Desu Seshu B. (Blacksburg VA) Si Jie (Blacksburg VA), Rare earth manganate films made by metalorganic decomposition or metalorganic chemical vapor deposition for nonvolatile.

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54. Shintani Masaki,JPX ; Shigeta Masanobu,JPX ; Nishihata Toshihiko,JPX ; Kurogane Hideo,JPX ; Honma Akira,JPX, Reflection-type display apparatus having antireflection films.

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55. Amanuma Kazushi,JPX, Semiconductor device and method of manufacturing the same.

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56. Hikosaka, Yukinobu; Ozaki, Yasutaka; Takai, Kazuaki, Semiconductor device and method of manufacturing the same.

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57. Kazushi Amanuma JP, Semiconductor device and method of manufacturing the same.

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58. Ishihara, Kazuya, Semiconductor memory device and method of fabricating the same.

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59. Mitarai Shun,JPX ; Ohnishi Shigeo,JPX ; Hara Tohru,JPX, Semiconductor memory device with less characteristic deterioration of dielectric thin film.

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60. Yen, Allen; Hui, Frank Yauchee; Yan, Yifeng Winston, Stacked structure for parallel capacitors and method of fabrication.

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61. Yamanobe, Tomomi, Wiring layer structure for ferroelectric capacitor.

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62. Yamanobe,Tomomi, Wiring layer structure for ferroelectric capacitor.

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