[특허]Shared register architecture for a dual-instruction-set CPU

Shared register architecture for a dual-instruction-set CPU 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-009/30
출원번호	US-0277962 (1994-07-20)
발명자 / 주소	Blomgren James S. (San Jose CA) Richter David E. (San Jose CA)
출원인 / 주소	Exponential Technology, Inc. (San Jose CA 02)
인용정보	피인용 횟수 : 109 인용 특허 : 0

초록 ▼

A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be transferred from a CISC program to a RISC program running on the CPU by using shared registers. The architecturally-defined registers in the CISC instruction set are merged or folded into some of the architecturally-defined registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the flags or condition code registers defined by each architecture are merged together so that CISC instructions and RISC instructions will implicitly update the same merged flags register when performing computational instructions. The RISC and CISC registers are folded together so that the CISC flags are at one end of the register while the frequently used RISC flags are at the other end, but the RISC instructions can read or write any bit in the merged register. The CISC code segment base address is stored in the RISC branch count register, while the CISC floating point instruction address is stored in the RISC branch link register. The general-purpose registers (GPR\s) are also merged together, allowing a CISC program to pass data to a RISC program merely by writing one of its GPR\s, switching control to the RISC program, and the RISC program reading one of its GPR\s that is merged with and corresponds to the CISC GPR that was written to by the CISC program.

대표청구항 ▼

A shared register system for a dual-instruction-set processor, the shared register system comprising: a shared register for storing information to be transferred between a first program comprised of instructions from a first instruction set and a second program comprised of instructions from a second instruction set, the first instruction set having a first encoding of operations to opcodes, the second instruction set having a second encoding of operations to opcodes, the first encoding of operations to opcodes being substantially independent from the second encoding of operations to opcodes; first means, coupled to the shared register, for accessing the shared register from the first instruction set, the first means writing information into the shared register responsive to a first subset of instructions from the first instruction set; and second means, coupled to the shared register, for accessing the shared register from the second instruction set, the second means reading information from the shared register responsive to a second subset of instructions from the second instruction set, wherein each instruction in the first subset of instructions from the first instruction set comprises a first opcode field indicating the operation encoded and a destination field specifying the shared register, and wherein each instruction in the second subset of instructions from the second instruction set comprises a second opcode field indicating the operation encoded and a source field specifying the shared register; wherein the first subset of instructions have first opcode fields with encodings for integer operations, arithmetic-logic-unit (ALU) operations, and register-to-register move operations and wherein the second subset of instructions have second opcode fields with encodings for integer operations, arithmetic-logic-unit (ALU) operations, and register-to-register move operations; wherein the shared register is in a plurality of general-purpose registers in the dual-instruction-set processor, the source field and the destination field selecting any one register in the plurality of general-purpose registers, the one register selected being the shared register for transferring information between the first program and the second program; wherein the first means for accessing the shared register from the first instruction set includes means for reading and means for writing information into the shared register; and wherein the second instruction set is a reduced instruction set computer (RISC) instruction set and the first instruction set is a complex instruction set computer (CISC) instruction set, whereby information is transferred from the first program to the second program using the shared register.

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Shared register architecture for a dual-instruction-set CPU 원문보기

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