[특허]System and method for controlling execution of nested loops in parallel in a computer including multiple processors, and

System and method for controlling execution of nested loops in parallel in a computer including multiple processors, and 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-009/45
출원번호	US-0395275 (1995-02-27)
발명자 / 주소	Harris Kevin W. (Nashua NH) Noyce William B. (Hollis NH)
출원인 / 주소	Digital Equipment Corporation (Maynard MA 02)
인용정보	피인용 횟수 : 28 인용 특허 : 0

초록 ▼

A system and method for controlling execution of nested loops in parallel in a computer including multiple processors, and a compiler for generating code therefor. The code enables the computer to operate in the following manner. Each processor processes an iteration of an outer loop in a set of nested loops. If the outer loop contains more iterations than processors in the system, the processors are initially assigned early iterations, and the later iterations are assigned to the processors as they finish their earlier iterations, until the processors have processed all of the iterations. Each processor, during processing of an outer loop iteration runs the iterations comprising the inner loop serially. In order to enforce dependencies between the loops, each processor reports its progress in its iterations of the inner loop to the processor executing the succeeding outer loop iteration. In addition, each processor, before processing the inner loop iterations of an assigned outer loop iteration, determines whether the processor computing the preceding outer loop is ahead or behind in processing its inner loop iteration by an amount which guarantees that dependencies will be enforced.

대표청구항 ▼

A method of compiling a nested loop program structure including an outer loop structure to be processed by a plurality of processors operating in parallel, each of said processors assigned to process a selected one of a plurality of outer loop iterations, and further including an inner loop structure to be processed in a plurality of inner loop iterations, the inner loop iterations corresponding to each said outer loop iteration being processed in series by the processor assigned to process the corresponding outer loop iteration, wherein at least one of the inner loop iterations is dependent upon a computation of another of the inner loop iterations in a preceding iteration of the outer loop iterations, the method comprising the steps, performed in a data processing system, of: A) extracting the outer loop structure from the nested loop structure; B) extracting the inner loop structure from the nested loop structure; C) generating a plurality of control structures each for enabling a corresponding one of said processors to perform a current outer loop iteration of the outer loop iterations and at least a current inner loop iteration of the inner loop iterations, each said control structure comprising a progress counter providing a count representing a number of inner loop iterations performed by the processor corresponding to said counter, said control structures enabling a current processor of the plurality of processors to perform the substeps of: i) waiting until a previous processor of the plurality of processors, performing a previous outer loop iteration that precedes the current outer loop iteration being performed by the current processor, generates a waiting report value indicating that the previous processor has completed performance of an inner loop iteration upon which the current inner loop iteration being performed by the current processor depends; ii) after the waiting step, performing the current inner loop iteration as defined by the inner loop structure; and iii) after the performing step, generating a next report value to indicate to a next processor of the plurality of processors that the current inner loop iteration has been completed by the current processor; D) wherein the waiting report value and the next report value are generated in response to the counts of the counters corresponding respectively to the previous processor and to the current processor.

이 특허를 인용한 특허 (28)

Fernando John S. ; Lemmon Frank T. ; Whalen Shaun P., Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously.
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Flachs, Brian; Johns, Charles Ray; Weigand, Ulrich, Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set.
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Bera,Rajendra K., Detection of reduction variables in an assignment statement.
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Ogasawara Takeshi,JPX ; Komats Hideaki,JPX, Method and apparatus for compilation of a data parallel language.
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Gupta Kumkum ; Touriguian Mihran ; Verbauwhede Ingrid ; Neff Harlan W., Method and apparatus for executing nested loops in a digital signal processor.
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Ryu, Soo Jung; Kim, Jeong Wook; Yoo, Dong Hoon; Kim, Hee Seok, Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array.
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Doshi Gautam ; Norin Robert, Method for software pipelining nested loops.
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Bera, Rajendra Kumar, Method, apparatus and computer program product for network design and analysis.
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Fuhler, Richard A.; Pennello, Thomas J.; Jalkut, Michael Lee; Warnes, Peter, Methods and apparatus for compiling instructions for a data processor.
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Fuhler,Richard A.; Pennello,Thomas J.; Jalkut,Michael Lee; Warnes,Peter, Methods and apparatus for compiling instructions for a data processor.
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Hardwick Jonathan C.,GBX, Nested parallel language preprocessor for converting parallel language programs into sequential code.
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Ogawa,Hajime; Takayama,Shuichi, Optimization apparatus that decreases delays in pipeline processing of loop and computer-readable storage medium storing optimization program.
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Funaki Hiroshi (Tokyo JPX), Optimizing compiler which generates multiple instruction streams to be executed in parallel.
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Ngo Viet N. ; Tsai Wei-Tek, Outer loop vectorization.
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Eichenberger, Alexandre E.; Flachs, Brian K.; Johns, Charles R.; Nutter, Mark R., Parallel execution unit that extracts data parallelism at runtime.
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Eichenberger, Alexandre E.; Flachs, Brian K.; Johns, Charles R.; Nutter, Mark R., Parallel execution unit that extracts data parallelism at runtime.
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Haselden, J. Kirk; Ivanov, Sergei, Parallel loops in a workflow.
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Bera, Rajendra K., Run-Time parallelization of loops in computer programs using bit vectors.
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Eichenberger, Alexandre E.; Flachs, Brian K.; Johns, Charles R.; Nutter, Mark R., Runtime extraction of data parallelism.
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Eichenberger, Alexandre E.; Flachs, Brian K.; Johns, Charles R.; Nutter, Mark R., Runtime extraction of data parallelism.
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Lau, David James; Pritchard, Jeffrey Orion; Molson, Philippe, Scheduling optimization of aliased pointers for implementation on programmable chips.
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Gabzdyl Rebecca,GBX ; McGovern Brian Patrick,GBX ; Vehvilainen Matti Juhani,FIX, System for executing nested software loops with tracking of loop nesting level.
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System and method for controlling execution of nested loops in parallel in a computer including multiple processors, and 원문보기

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