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Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0207012 (1994-03-04)
발명자 / 주소
  • Costello John C. (San Jose CA) Patel Rakesh H. (Santa Clara CA)
출원인 / 주소
  • Altera Corporation (San Jose CA 02)
인용정보 피인용 횟수 : 189  인용 특허 : 0

초록 ▼

A programmable logic device is provided that contains a plurality of logic array blocks arranged in rows and columns. The logic array blocks are interconnected with horizontal conductors in each row and vertical conductors in each column. The logic array blocks and the interconnections between condu

대표청구항 ▼

A programmable logic device comprising: a plurality of rows and columns of logic array blocks, each logic array block having at least one input terminal for receiving input signals and at least one output terminal, each logic array block being programmable to produce output signals at the output ter

이 특허를 인용한 특허 (189)

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