초록 ▼

A programmable PCM/TDM demultiplexer including an FA function unit including Frame Alignment Logic (FAL) hardware controlled by a Programmable Frame Alignment Controller (PFAC), and accompanied by a DECommutation and dejustification (DEC) function unit including Output Logic Hardware (OLH) controlle

A programmable PCM/TDM demultiplexer including an FA function unit including Frame Alignment Logic (FAL) hardware controlled by a Programmable Frame Alignment Controller (PFAC), and accompanied by a DECommutation and dejustification (DEC) function unit including Output Logic Hardware (OLH) controlled by a Programmable Decommutator Sequencer (PDS) controlled in turn by a Programmable Decommutator Sequencer Controller (PDSC).

대표청구항 ▼

Apparatus for demultiplexing a PCM/TDM input data signal containing frame alignment signals that are used to achieve frame synchronization, said apparatus comprising: frame alignment logic means for receiving said PCM/TDM input data signal, a bit clock signal having a predetermined bit clock rate de

Apparatus for demultiplexing a PCM/TDM input data signal containing frame alignment signals that are used to achieve frame synchronization, said apparatus comprising: frame alignment logic means for receiving said PCM/TDM input data signal, a bit clock signal having a predetermined bit clock rate derived from said input data signal, and a current instruction signal, for detecting said frame alignment signals, for generating a frame synchronization signal in response to the detection of a boundary of a frame in said input data signal, and for generating a frame alignment status signal; a programmable frame alignment controller for receiving said bit clock signal and said frame alignment status signal, for generating said current instruction signal, and for controlling said frame alignment logic means; output logic means for receiving said bit clock signal, said input data signal, and sequences of control words for decommutating sequences of bit formats that repeat within said frame, and for generating an output tributary signal, a data valid signal indicating that an output tributary signal has been generated, and a dejustification status signal indicative of a dejustification state of the output logic means; a programmable sequencer for receiving said bit clock signal, and a next sequence instruction signal, for generating said sequences of control words that decommutate the sequences of bit formats that repeat within said frame, and for generating an instruction done signal; and a programmable sequencer controller for receiving said frame synchronization signal, said dejustification status signal, and said instruction done signal, and for generating said next sequence instruction signal to cause said programmable sequencer to generate said sequences of control words; and wherein said output logic means and said programmable sequencer are caused to operate at the bit clock rate of said bit clock signal, and and wherein said programmable sequencer controller is caused to operate at a fraction of said bit clock rate.