초록 ▼

A memory system including a memory array having at least two pairs of data lines, first and second data lines, that correspond to columns in the memory array. A first stage is included having inputs connected to the two pairs of data lines. The first stage also has a pair of output lines, a true out

A memory system including a memory array having at least two pairs of data lines, first and second data lines, that correspond to columns in the memory array. A first stage is included having inputs connected to the two pairs of data lines. The first stage also has a pair of output lines, a true output lines and a complement output line, wherein output signals generated in the output lines are controlled by a first and second set of transistors. Each transistor in the first set has a gate connected to one of the input lines, and each transistor in the second set is connected in series with one of the transistors in the first set and may be selectively turned on and turned off, wherein of one of the two pairs of data lines may be selected by turning transistors on and off in the second set.

대표청구항 ▼

A memory system comprising: a memory array having at least first and second pairs of data lines corresponding to columns in the memory array; and a multiplexing sense amplifier including a selection stage having input lines connected to the first and second pairs of data lines, the selection stage a

A memory system comprising: a memory array having at least first and second pairs of data lines corresponding to columns in the memory array; and a multiplexing sense amplifier including a selection stage having input lines connected to the first and second pairs of data lines, the selection stage also having a true output line and a complement output line, wherein output signals generated in the output lines are controlled by a first and second set of transistors, wherein each transistor in the first set has a gate connected to one of the input lines and each transistor in the second set is connected in series with one of the transistors in the first set and may be selectively turned on and turned off, wherein one of the two pairs of data lines may be selected by turning transistors on and off in the second set, wherein said multiplexing sense amplifier includes a common current source provided by a control transistor having a first source/drain connected to a power supply voltage and a second source/drain connected to the first and second sets of transistors by a common node, wherein the multiplexing sense amplifier may be enabled and disabled by turning the control transistor on and off, and wherein the selection stage further includes a p-channel cross-coupled amplifier.