$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

SOI MOSFET with floating gate 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/78
출원번호 US-0160885 (1993-12-03)
우선권정보 JP-0325783 (1992-12-04); JP-0131864 (1993-06-02)
발명자 / 주소
  • Tsuruta Kazuhiro (Obu JPX) Himi Hiroaki (Nagoya JPX) Asai Akiyoshi (Aichi JPX) Fujino Seiji (Toyota JPX)
출원인 / 주소
  • Nippondenso Co., Ltd. (Kariya JPX 03)
인용정보 피인용 횟수 : 72  인용 특허 : 0

초록 ▼

A semiconductor device of an SOIMOSFET comprising a semiconductor substrate, an insulating layer and a thin film single-crystalline semiconductor layer, the insulating layer containing a floating electrically conductive layer buried therein at a portion corresponding to the channel, the floating ele

대표청구항 ▼

A semiconductor device comprising a semiconductor substrate, a thin film single-crystalline semiconductor layer with an insulating layer interposed therebetween, the insulating layer containing a floating electroconductive layer buried therein, a MOSFET comprising source and drain regions in the thi

이 특허를 인용한 특허 (72)

  1. Willard, Simon Edward; Ranta, Tero Tapio, AC coupling modules for bias ladders.
    상세보기
  2. Chan Kevin Kok ; D'Emic Christopher Peter ; Jones Erin Catherine ; Solomon Paul Michael ; Tiwari Sandip, Back-plane for semiconductor device.
    상세보기
  3. Dribinsky, Alexander; Kim, Tae Youn; Kelly, Dylan J.; Brindle, Christopher N., Circuit and method for controlling charge injection in radio frequency switches.
    상세보기
  4. Shapiro, Eric S.; Allison, Matt, Circuit and method for improving ESD tolerance and switching speed.
    상세보기
  5. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
    상세보기
  6. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
    상세보기
  7. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
    상세보기
  8. Bawell, Shawn; Broughton, Robert; Bacon, Peter; Greene, Robert W.; Ranta, Tero Tapio, Digitally tuned capacitors with tapered and reconfigurable quality factors.
    상세보기
  9. Li, Ruigang; Zhou, Jingrong; Wu, David Donggang; Shi, Zhonghai; Buller, James F.; Michael, Mark W.; Sultan, Akif; Hause, Fred, Electronic device and method of biasing.
    상세보기
  10. Kwon Oh Won,KRX, Flash memory cell.
    상세보기
  11. Hagemeyer,Peter; Langheinrich,Wolfram, Flash memory cell with buried floating gate and method for operating such a flash memory cell.
    상세보기
  12. Yang, Ki Hong; Park, Sang Wook, Flash memory device having resistivity measurement pattern and method of forming the same.
    상세보기
  13. Yang,Ki Hong; Park,Sang Wook, Flash memory device having resistivity measurement pattern and method of forming the same.
    상세보기
  14. Kumar Arvind ; Tiwari Sandip, Floating back gate electrically erasable programmable read-only memory (EEPROM).
    상세보기
  15. Arvind Kumar ; Sandip Tiwari, Floating back gate electrically erasable programmable read-only memory(EEPROM).
    상세보기
  16. Oyama Kenichi,JPX, Floating gate type non-volatile semiconductor memory for storing multi-value information.
    상세보기
  17. Bhattacharyya,Arup, Gated lateral thyristor-based random access memory cell (GLTRAM).
    상세보기
  18. Bhattacharyya,Arup, Gated lateral thyristor-based random access memory cell (GLTRAM).
    상세보기
  19. Bryant, Andres; Nowak, Edward J.; Williams, Richard Q., High performance capacitors in planar back gates CMOS.
    상세보기
  20. Bhattacharyya, Arup, High-performance one-transistor memory cell.
    상세보기
  21. Bhattacharyya, Arup, High-performance one-transistor memory cell.
    상세보기
  22. Nobbe, Dan William; Olson, Chris; Kovac, David, Hot carrier injection compensation.
    상세보기
  23. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
    상세보기
  24. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
    상세보기
  25. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
    상세보기
  26. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
    상세보기
  27. Lombardo, Salvatore; Gerardi, Cosimo; Crupi, Isodiana; Melanotte, Massimo, Memory cell structure integrated on semiconductor.
    상세보기
  28. Bhattacharyya, Arup, Memory cell with negative differential resistance.
    상세보기
  29. Bhattacharyya,Arup, Memory cell with trenched gated thyristor.
    상세보기
  30. Bhattacharyya,Arup, Memory cell with trenched gated thyristor.
    상세보기
  31. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide nanolaminates.
    상세보기
  32. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide nanolaminates.
    상세보기
  33. Ranta, Tero Tapio, Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device.
    상세보기
  34. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
    상세보기
  35. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
    상세보기
  36. Brindle, Christopher N.; Deng, Jie; Genc, Alper; Yang, Chieh-Kai, Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction.
    상세보기
  37. Brindle, Christopher N.; Deng, Jie; Genc, Alper; Yang, Chieh-Kai, Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction.
    상세보기
  38. Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
    상세보기
  39. Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
    상세보기
  40. Ohno Yasuo,JPX, Method for forming a field-effect transistor having difference in capacitance between source and drain with respect to.
    상세보기
  41. Bhattacharyya, Arup, Method for forming a high-performance one-transistor memory cell.
    상세보기
  42. Yamazaki, Shunpei; Kusumoto, Naoto; Teramoto, Satoshi, Method for producing semiconductor device.
    상세보기
  43. Hisayoshi Yamoto JP; Hideo Yamanaka JP; Yuichi Satou JP; Hajime Yagi JP, Method of forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device.
    상세보기
  44. Ajmera, Atul; Leobandung, Effendi; Rausch, Werner; Schepis, Dominic J.; Shahidi, Ghavam G., Method of integrating substrate contact on SOI wafers with STI process.
    상세보기
  45. Bhattacharyya, Arup, Method of making a one transistor SOI non-volatile random access memory cell.
    상세보기
  46. Reedy, Ronald Eugene; Nobbe, Dan William; Ranta, Tero Tapio; Liss, Cheryl V.; Kovac, David, Methods and apparatuses for use in tuning reactance in a circuit device.
    상세보기
  47. Bhattacharyya, Arup, One transistor SOI non-volatile random access memory cell.
    상세보기
  48. Bhattacharyya, Arup, One transistor SOI non-volatile random access memory cell.
    상세보기
  49. Bhattacharyya,Arup, One transistor SOI non-volatile random access memory cell.
    상세보기
  50. Bhattacharyya,Arup, One transistor SOI non-volatile random access memory cell.
    상세보기
  51. Bhattacharyya,Arup, One transistor SOI non-volatile random access memory cell.
    상세보기
  52. Bhattacharyya, Arup, One-device non-volatile random access memory cell.
    상세보기
  53. Chung, In-Jae; Kim, Ki-Yong; Han, Chang-Wook; Hwang, Kwang-Jo, Organic electroluminescent display device and method of fabricating the same.
    상세보기
  54. Ranta, Tero Tapio, Positive logic digitally tunable capacitor.
    상세보기
  55. Facchini, Marc; Bacon, Peter, Power splitter with programmable output phase shift.
    상세보기
  56. Cai, Jin; Dennard, Robert H.; Khakifirooz, Ali; Ning, Tak H.; Yau, Jeng-Bang, SOI CMOS structure having programmable floating backplate.
    상세보기
  57. Shigenobu Maeda JP; Tadashi Nishimura JP; Kazuhito Tsutsumi JP; Shigeto Maegawa JP; Yuuichi Hirano JP, SOI based transistor inside an insulation layer with conductive bump on the insulation layer.
    상세보기
  58. Hogyoku, Michiru, Semiconductor devices including a silicon-on-insulator layer.
    상세보기
  59. Olson, Chris, Semiconductor devices with switchable ground-body connection.
    상세보기
  60. Morinaka Hiroyuki,JPX ; Ueda Kimio,JPX ; Mashiko Koichiro,JPX, Semiconductor integrated circuit device, method for manufacturing the same, and logical circuit.
    상세보기
  61. Carroll, Michael; Kerr, Daniel Charles; Iversen, Christian Rye; Mason, Philip; Costa, Julio; Spears, Edward T., Semiconductor radio frequency switch with body contact.
    상세보기
  62. Ohkubo, Yasunori, Semiconductor substrate, semiconductor device, and processes of production of same.
    상세보기
  63. Shunpei Yamazaki JP; Akiharu Miyanaga JP; Jun Koyama JP; Takeshi Fukunaga JP, Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method.
    상세보기
  64. Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method.
    상세보기
  65. Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method.
    상세보기
  66. Aitken John M. ; Mittl Steven W. ; Strong Alvin W., Silicon-on-insulator non-volatile random access memory device.
    상세보기
  67. Yamazaki,Shunpei; Miyanaga,Akiharu; Koyama,Jun; Fukunaga,Takeshi, Static random access memory using thin film transistors.
    상세보기
  68. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
    상세보기
  69. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
    상세보기
  70. Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Thin film semiconductor device and its manufacturing method.
    상세보기
  71. Englekirk, Robert Mark, Tuning capacitance to enhance FET stack voltage withstand.
    상세보기
  72. Englekirk, Robert Mark, Tuning capacitance to enhance FET stack voltage withstand.
    상세보기

관련 콘텐츠

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로