초록 ▼

This invention involves transducing and monitoring the power being delivered by an electric generator to a power bus by using a monitor which includes an embedded microprocessor in the memory of which are stored reference digital numbers that correspond to the generator\s nominal power, and to the c

This invention involves transducing and monitoring the power being delivered by an electric generator to a power bus by using a monitor which includes an embedded microprocessor in the memory of which are stored reference digital numbers that correspond to the generator\s nominal power, and to the components of the nominal power including output power. The generator\s voltage and current signals are sensed and then shaped for use by the microprocessor wherein they are digitized into a first set of digital numbers. Preferably, the first set of digital numbers is converted into pulse-width modulated (PWM) square-wave signals, which are demodulated into DC current signals that are indicative of the power and the components of power being delivered by the electric generator to its power bus. The microprocessor digitizes the square wave signals into a second set of digital numbers, and calculates from the first and from the second sets of digital numbers real time digital numbers. Preferably a microcontroller is also embedded with the microprocessor to compare the calculated real time digital numbers with their corresponding reference digital numbers and to generate control signals to selectively actuate circuit breakers which interconnect the generator and its loads to the power bus.

대표청구항 ▼

In a power measuring and control system (20) for measuring and controlling the output power of a multiphase AC generator (21) and its prime mover; said generator being connected in parallel with another multiphase AC generator (21′) through a power bus (24) having at least three phase lines fa,fb,fc

In a power measuring and control system (20) for measuring and controlling the output power of a multiphase AC generator (21) and its prime mover; said generator being connected in parallel with another multiphase AC generator (21′) through a power bus (24) having at least three phase lines fa,fb,fc for feeding power to loads (23a-23c) through connect/disconnect means (80d-82d); each one of said generators having distinct criteria for the nominal output power, the magnitude and sign of the power factor (PF), the RMS voltage Vrms, the RMS current Irms, and their fundamental frequency f; and said criteria having specified, allowable deviation ranges within set trigger points, the improvement comprising: voltage sensing means (25,25′) for sensing between said phases fa,fb and fb,fc the instantaneous sinusoidal voltage signals Vab,Vbc (30,32), respectively, having a fundamental frequency f; current sensing means (26,26′) for sensing the instantaneous sinusoidal current signals Ia,Ic (33,35) in said phases fa,fc, respectively; signal shaper means (27,28,29,50,51,54,55) for shifting, band-limiting and attenuating said instantaneous voltage and current signals and for producing therefrom: (a) corresponding attenuated sinusoidal voltage and current signals Vab,Vbc (38,39) and Ia,Ic (40, 41), (b) corresponding, respective, synchronized, voltage and current square-wave signals Vab,Vbc,Ia,Ic (42,43,44,45) containing information on said fundamental frequency f, and (c) a square wave signal Vab (46) having a fixed, high-multiple frequency of said fundamental frequency f; said shaper means (27) having two voltage channels (28) and two current channels (29), each channel having phase-locked loops (PLL) (51) for generating from said attenuated sinusoidal signals Vab,Vbc,Ia,Ic said square wave signals Vab,Vbc,Ia,Ic (42-46); micro-processor/micro-controller (M-P/M-C) means (22) including: an electronic read-only memory (ROM) (60), a random-access memory (RAM) (61), analog-to-digital (A/D) converter means, high-speed inputs (HSIs) for receiving said square wave signals Vab,Vbc,Ia,Ic (42-45), an external interrupt (EXINT) input for receiving said high frequency square wave signal Vab (46), high-speed outputs (HSOs), and hi-directional input-output (I/O) ports (P1); a configuration network (62) coupled to said ROM (60) and to said RAM (61) through an address/data bus (63) for configuring said micro-processor/micro-controller means (22) to control the output power of its associated generator in accordance with said generation\s particular criteria values and set points; said network (62) including binary-coded rotary configuration switches, each switch being mechanically adjustable for a particular criterion value and its set points, and each switch acting as a mechanical ROM occupying memory address space in said electronic ROM and being readable as an electronic ROM; said (A/D) converter means digitizing said attenuated sinusoidal voltage and current signals Vab,Vbc,Ia,Ic (38,39,40,41); said M-P means (22) under the control of software digitizing said square wave signals Vab,Vbc,Ia,Ic (42-45) into respective digital representations thereof, sampling, N times per cycle, starting when said high-frequency square wave signal (46) transits from low to high, the instantaneous digital values of vab,vbc and of ia,ic, for each sample of said digitized sinusoidal voltage and current signals, calculating for each sample the instantaneous power pas in said phase fa from pas=(vabia) and the instantaneous power pcs in said phase fc from pcs=(vbcic), calculating the mean power per cycle pam/cyc in said phase fa from pam/cyc=Sas/N, the mean power per cycle pcm/cyc in said phase fc from pcm/cyc=Scs/N, and the resultant mean power per cycle of Pm/cyc from Pm/cyc=pam+pcm, digitally calculating 1) the root-mean-square RMS value of the voltage per cycle between (a) said phases fa, fb from vabmrms/cyc=√Sab2/N, (b) said phases fb,fc from vbcmrms/cyc=√Sbc2/N, 2) the root-mean-square RMS value of the current per cycle in (a) said phase fa from iamrms/cyc=√Sa2/N, (b) said phase fc from icmrms/cyc=√rc2/N, 3) the mean root-mean-square RMS value of the voltage per cycle on said bus from Vmrms/cyc=(Yabrms+vbcrms)/2, 4) the mean root-mean-square RMS value of the current per cycle in said bus from Imrms/cyc=(iarms+icrms)/2, and 5) the power factor value per cycle in said bus from PF/cyc=Pm/(1.73 Vmrms×Imrms), said PF/cyc being positive (+) when said square wave signals Ia,Ic (40,41) lead said square wave signals Vab,Vbc (38,39), respectively, and, conversely, said PF/cyc being negative (-) when said square wave signals Ia,Ic (40,41) lag said square wave signals Vab,Vbc; said (M-P/M-C) means (22) being, in use, under the control of said software and of said settings on said configuration switches for continuously digitally comparing one or more of said measured components of power, including: said instantaneous phase powers pa and pc, said mean power per cycle Pm, said phase RMS voltages per cycle vabmrms and vbcmrms, said mean RMS voltage per cycle vmrms, said RMS phase currents per cycle Iamrms and Icmrms, said mean RMS current per cycle Imrms, and said power factor per cycle PF and its sign (+/-), against their corresponding comparable criteria values stored in said electronic ROM, and when the result of such comparison yields a result which is either under or over one of said stored set point values in said ROM, said M-C means is triggered to output from said I/O bi-directional ports a digital control signal tripping, in a timely fashion, one or more of said connect/disconnect means (80d-82d) thereby causing appropriate successive sheddings of said loads from said bus or, if said load sheddings are insufficient, to completely break the tie between the controlled overloaded generator (21) and said power bus (24) so as to reduce from said overloaded generator a temporary, excessive, high-power load demand, and protecting the remaining generator (21′) and its prime mover; and adjustable delay means for delaying said load sheddings by discrete time intervals before generating said control signals.