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Semiconductor device having a planarized surface 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/321
  • H01L-023/522
출원번호 US-0298296 (1994-08-31)
우선권정보 JP-0025220 (1994-02-23)
발명자 / 주소
  • Hayashide Yoshio (Hyogo JPX)
출원인 / 주소
  • Mitsubishi Denki Kabushiki Kaisha (Tokyo JPX 03)
인용정보 피인용 횟수 : 36  인용 특허 : 0

초록

An object of the present invention is to completely reduce a difference in level in a short time at a convex pattern spreading horizontally on a large scale and obtain a semiconductor device having a planarized surface. An insulating film is formed on a semiconductor substrate to cover a horizontall

대표청구항

A semiconductor device having a planarized surface, comprising: a semiconductor substrate; an interconnection layer portion provided on a surface of said semiconductor substrate and having a plurality of elements of at least one interconnection layer spreading horizontally, comprising a high density

이 특허를 인용한 특허 (36)

  1. Jacob Daniel Haskell ; Rong Hsu, Combination CMP-etch method for forming a thin planar layer over the surface of a device.
  2. Burnham, Jay; Cartier, Eduard A.; Ference, Thomas G.; Mittl, Steven W.; Stamper, Anthony K., Deuterium reservoirs and ingress paths.
  3. Burnham, Jay; Cartier, Eduard A.; Ference, Thomas G.; Mittl, Steven W.; Stamper, Anthony K., Deuterium reservoirs and ingress paths.
  4. Ikemasu,Shinichiroh; Okawa,Narumi, Highly integrated and reliable DRAM.
  5. Ikemasu, Shinichiroh; Okawa, Narumi, Highly integrated and reliable DRAM and its manufacture.
  6. Ikemasu, Shinichiroh; Okawa, Narumi, Highly integrated and reliable DRAM and its manufacture.
  7. Ikemasu, Shinichiroh; Okawa, Narumi, Insulation structure for wiring which is suitable for self-aligned contact and multilevel wiring.
  8. Berthold,J철rg; Schwarzl,Siegfried, Integrated electrical circuit and method for fabricating it.
  9. Chiang Chien ; Fraser David B., Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics.
  10. Chiang Chien ; Fraser David B., Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics.
  11. Oda Noriaki,JPX, Interconnection layer structure in a semiconductor integrated circuit device having macro cell regions.
  12. Gonzalez, Fernando; Sandhu, Gurtej S.; Violette, Mike P., Memory devices with buried lines.
  13. Takahashi Hiroshi,JPX ; Tokunaga Kazuhiko,JPX ; Yoshigoe Shunichi,JPX, Method of etching back layer on substrate.
  14. Zhao Ji ; Teng Chih Sieh, Methods for making VLSI capacitors and high Q VLSI inductors using metal-filled via plugs.
  15. Nam, Gee-won; Park, Gi-jong; Hwang, Hong-kyu; Bae, Jun-shik; Park, Young-rae; Kim, Jung-yup; Yoon, Bo-un; Hah, Sang-rok, Methods of planarizing insulating layers on regions having different etching rates.
  16. Lin Yung-Fa,TWX, Optimized process for creating and passivating a metal pillar via structure located between two metal interconnect stru.
  17. Shigeo Moriyama JP; Katsuhiko Yamaguchi JP; Yoshio Homma JP; Sunao Matsubara JP; Yoshihiro Ishida JP; Ryousei Kawa-ai JP, Polishing method and apparatus.
  18. Park, Sung Kee, Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film.
  19. Oyamatsu Hisato,JPX ; Murota Masayuki,JPX, Semiconductor device having structure suitable for CMP process.
  20. Asai Akiyoshi,JPX ; Ohya Nobuyuki,JPX ; Katada Mitsutaka,JPX, Semiconductor device with conductive connecting layer and abutting insulator section made of oxide of same material.
  21. Eimori,Takahisa, Semiconductor device with multiple layer insulating film.
  22. Ohno Yoshikazu,JPX, Semiconductor device with short circuit prevention and method of manufacturing thereof.
  23. Mizushima Kazuyuki,JPX, Semiconductor integrated circuit device having multi-level wiring structure without dot pattern.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  28. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  29. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  30. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  31. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  32. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  33. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  34. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  35. Zhao Ji ; Teng Chih Sieh, VLSI capacitors and high Q VLSI inductors using metal-filled via plugs.
  36. Wang Xiewen, Water vapor annealing process.
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