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Method for connection of signals to an integrated circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-003/34
출원번호 US-0239796 (1994-05-09)
발명자 / 주소
  • Gehman
  • Jr. John B. (Scottsdale AZ) O\Connell Richard P. (Scottsdale AZ)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 100  인용 특허 : 0

초록 ▼

A method and apparatus for connecting signal leads to an integrated circuit transmits a distribution signal on a lead. A substrate is provided with leads interconnecting a number of bonding pads. The integrated circuit has a corresponding number of bonding pads. An insulation layer is interposed bet

대표청구항 ▼

A method for connecting a clock signal to an integrated circuit comprising the steps of: providing a substrate with at least one distribution bonding pad connected to a first set of bonding pads; providing the clock signal on a distribution lead, said distribution lead being located within the subst

이 특허를 인용한 특허 (100)

  1. Schmausser Stefan,DEX ; Gruber Otto,DEX ; Fischer Siegfried,DEX ; Juri Walter,DEX ; Barchmann Bernd,DEX ; Winterer Jurgen,DEX ; Petz Martin,DEX ; Steinbichler Jurgen,DEX ; Schlogel Xaver,DEX ; Voggen, Arrangement of electronic components on a bearer strip.
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  4. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
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  10. Siniaguine, Oleg, Clock distribution networks and conductive lines in semiconductor integrated circuits.
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  11. Siniaguine,Oleg, Clock distribution networks and conductive lines in semiconductor integrated circuits.
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  12. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
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  23. Rao Valluri R. ; Greason Jeffrey K. ; Livengood Richard H., Method and apparatus for distributing a clock on the silicon backside of an integrated circuit.
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  25. Valluri R. Rao ; Jeffrey K. Greason ; Richard H. Livengood, Method for distributing a clock on the silicon backside of an integrated circuit.
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  38. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  62. Rao Valluri R. ; Greason Jeffrey K. ; Livengood Richard H., Signal distribution network on backside of substrate.
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  63. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  79. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  80. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  82. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  83. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  84. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  85. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  87. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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