[특허]Method of forming flat surface of insulator film of semiconductor device

Method of forming flat surface of insulator film of semiconductor device 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/302 H01L-021/463
출원번호	US-0283295 (1994-07-28)
우선권정보	JP-0207218 (1993-07-29)
발명자 / 주소	Murase Hiroshi (Tokyo JPX)
출원인 / 주소	NEC Corporation (Tokyo JPX 03)
인용정보	피인용 횟수 : 17 인용 특허 : 0

초록 ▼

A method of forming a flat surface of an insulator film of a semiconductor device, providing no excessive polishing, polishing waste that is easily removed and an extensive flat surface of the insulator film. A first wiring film is formed on or over a semiconductor substrate and a first insulator film is formed on the first wiring film. The first insulator film and the first wiring film are patterned to a given shape in the same patterning process. A second insulator film is formed on the first insulator film thus patterned. The second insulator film is relatively higher in polishing rate than the first insulator film. Then, a surface of the second insulator film is polished to be flattened under pressure until the first insulator film is exposed. As the first and second insulator films, a silicon nitride film and a silicon dioxide film are preferably used, respectively.

대표청구항 ▼

A method of forming a flat surface of an insulator film of a semiconductor device, comprising the steps of: forming a first wiring film on a semiconductor substrate; forming a first insulator film on said first wiring film; forming a patterned resist film on said first insulator film; patterning said first insulator film to a pattern using said patterned resist film as a mask; patterning said first wiring film using said patterned first insulator film as a mask; removing said patterned resist film to produce said patterned first wiring film formed on said substrate and said patterned first insulator film formed over said patterned first wiring film, said patterned first wiring film and said patterned first insulator film having spaces formed therein; forming a second insulator film on said patterned first insulator film to fill said spaces with said second insulator film, said first insulator film being relatively lower in polishing rate than said second insulator film, said second insulator film having a surface being uneven due to said patterned first wiring film and said patterned first insulator film; and polishing said uneven surface of said second insulator film under pressure until said first insulator film is exposed to flatten said uneven surface of said second insulator film, said spaces remaining filled with said second insulator film; wherein said patterned first wiring film has a first wiring region and a second wiring region, said first wiring region being relatively lower in polishing rate than said second wiring region; and wherein said patterned first insulator film acts as a polishing stopper in said second wiring region to compensate for a difference in polishing rate between said first wiring region and said second wiring region during polishing.

이 특허를 인용한 특허 (17)

Hosali Sharath D. ; Sethuraman Anantha R. ; Wang Jiun-Fang ; Cook Lee Melbourne, Composition and method for polishing a composite of silica and silicon nitride.
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Hosali Sharath D. ; Sethuraman Anantha R. ; Wang Jiun-Fang ; Cook Lee Melbourne ; Oliver Michael R., Composition and method for polishing a composite of silica and silicon nitride.
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Hosali Sharath D. ; Sethuraman Anantha R. ; Wang Jiun-Fang ; Cook Lee Melbourne ; Oliver Michael R., Composition and method for polishing a composite of silica and silicon nitride.
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Hosali Sharath D. ; Sethuraman Anantha R. ; Wang Jiun-Fang ; Cook Lee Melbourne, Composition for polishing a composite of silica and silicon nitride.
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Kishimoto Koji,JPX, Flat interlayer insulating film suitable for multi-layer wiring.
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Harvey Ian, Integrated circuit device interconnection techniques.
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Sandhu Gurtej S. ; Sharan Sujit, Low scratch density chemical mechanical planarization process.
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Murase Hiroshi (Tokyo JPX), Method for fabricating semiconductor device with chemical-mechanical polishing process for planarization of interlayer i.
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Hachiya Takayo,JPX ; Yabuki Moto,JPX ; Kamijou Hiroyuki,JPX, Method for manufacturing a semiconductor device.
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Wang Brian,TWX ; Hsu Chih-Ching,TWX, Method for manufacturing even dielectric layer.
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Chris Ting TW; Janet Yu TW, Method for metal etch using a dielectric hard mask.
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Meikle Scott G., Method of chemical mechanical polishing for dielectric layers.
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Jan V. Shubert ; Glen Wada ; Mansour Moinpour ; Yang-Chin Shih ; Ken Schatz, Passivation for tight metal geometry.
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Dunton Samuel V. ; Lee Ming-Yi, Planarization system.
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Greco Nancy Anne ; Greco Stephen Edward, Process for reducing pattern factor effects in CMP planarization.
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Srikanteswara Dakshina-Murthy ; Paul R. Besser ; Jonathan B. Smith ; Eric M. Apelgren ; Christian Zistl DE; Jeremy I. Martin ; Lie Larry Zhao ; Nicholas John Kepler, Resist trim process to define small openings in dielectric layers.
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Wieczorek, Karsten; Burbach, Gert; Feudel, Thomas, Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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Method of forming flat surface of insulator film of semiconductor device 원문보기

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Method of forming flat surface of insulator film of semiconductor device 원문보기

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