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Data output buffer control circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
출원번호 US-0382757 (1995-02-02)
우선권정보 KR-0001939 (1994-02-03)
발명자 / 주소
  • Kwon Gi W. (Kyoungki-do KRX)
출원인 / 주소
  • Hyundai Electronics Industries Co., Ltd. (Kyoungki-do KRX 03)
인용정보 피인용 횟수 : 40  인용 특허 : 0

초록 ▼

In a semiconductor memory device having a plurality of memory cells and a data output buffer for transferring a data signal from the memory cells to external peripheral circuits, a circuit for controlling the data output buffer, comprising a address transition detector for detecting a transition of

대표청구항 ▼

In a semiconductor memory device having a plurality of memory cells and a data output buffer for transferring a data signal from said memory cells to external peripheral circuits, a circuit for controlling said data output buffer, comprising: address transition detection means for detecting a transi

이 특허를 인용한 특허 (40)

  1. Dean Gans ; Eric J. Stave ; Joseph Thomas Pawlowski, Adjustable I/O timing from externally applied voltage.
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  2. Patrick J. Mullarkey, Apparatus for adjusting delay of a clock signal relative to a data signal.
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  3. Mullarkey, Patrick J., Computer system having memory device with adjustable data clocking using pass gates.
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  4. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
    상세보기
  5. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
    상세보기
  6. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
    상세보기
  7. Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
    상세보기
  8. Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
    상세보기
  9. Lee,Terry R.; Jeddeloh,Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
    상세보기
  10. Keeth, Brent, Memory system with dynamic timing correction.
    상세보기
  11. Keeth, Brent; Manning, Troy A., Method and apparatus for adjusting the timing of signals over fine and coarse ranges.
    상세보기
  12. Keeth, Brent; Lee, Terry R.; Ryan, Kevin; Manning, Troy A., Method and apparatus for bit-to-bit timing correction of a high speed memory bus.
    상세보기
  13. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
    상세보기
  14. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
    상세보기
  15. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
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  16. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
    상세보기
  17. Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.
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  18. Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.
    상세보기
  19. Ronnie M. Harrison, Method and apparatus for generating a phase dependent control signal.
    상세보기
  20. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
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  21. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
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  22. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
    상세보기
  23. Harrison,Ronnie M., Method and apparatus for generating a sequence of clock signals.
    상세보기
  24. Manning, Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
    상세보기
  25. Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
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  26. Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
    상세보기
  27. Troy A. Manning, Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
    상세보기
  28. Stevens William A., Method and apparatus for levelizing transfer delays for a channel of devices such as memory devices in a memory subsystem.
    상세보기
  29. Johnson, Brian; Harrison, Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.
    상세보기
  30. Johnson,Brian; Harrison,Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.
    상세보기
  31. Manning, Troy A., Method for generating expect data from a captured bit pattern, and memory device using same.
    상세보기
  32. Hunt Jeffery Scott ; Anumula Sudhaker Reddy ; Srikrishna Ajay ; Waldrip Jeffrey W. ; Saripella Satish C., Method, architecture and circuit for writing to a memory.
    상세보기
  33. Hunt Jeffery Scott ; Anumula Sudhaker Reddy ; Srikrishna Ajay ; Waldrip Jeffrey W. ; Saripella Satish C., Method, architecture and circuit for writing to and reading from a memory during a single cycle.
    상세보기
  34. Yamaguchi Takashi,JPX, Output synchronization method and apparatus in a memory system utilizing small buffer size.
    상세보기
  35. Fagan, John L.; Bossard, Mark, Selectable delay pulse generator.
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  36. Komarek James A. (Balboa Beach CA) Tanner Scott B. (Irvine CA) Padgett Clarence W. (Westminster CA) Minney Jack L. (Irvine CA), Semiconductor read-only VLSI memory.
    상세보기
  37. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
    상세보기
  38. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
    상세보기
  39. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
    상세보기
  40. Atsumasa Sako JP, Variable delay circuit and semiconductor integrated circuit having the same.
    상세보기

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