$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Multi-layer substrate

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/20
출원번호 US-0291508 (1994-08-18)
우선권정보 JP-0052865 (1992-03-11); JP-0068009 (1992-03-26)
발명자 / 주소
  • Miyagi Takeshi (Fujisawa JPX) Matsumoto Kazuhiro (Yokohama JPX) Sasaki Tomiya (Yokohama JPX) Iwasaki Hideo (Kawasaki JPX) Hisano Katsumi (Yokohama JPX)
출원인 / 주소
  • Kabushiki Kaisha Toshiba (Kanagawa JPX 03)
인용정보 피인용 횟수 : 49  인용 특허 : 0

초록

A multi-layer wiring substrate includes an aluminum nitride ceramic substrate, a multi-layer wiring part having an electric insulating layer of an organic polymer, a die pad for mounting thereon an electronic part, and a thermal via of a column shape for effectively dissipating heat generated in the

대표청구항

A multi-layer wiring substrate comprising: a ceramic substrate; a wiring layer comprising a wiring formed in an electrical insulating material, the wiring layer being integrally formed on the ceramic substrate; a die pad for mounting thereon an electronic part, the die pad being provided on a surfac

이 특허를 인용한 특허 (49)

  1. Andry, Paul S.; Cotte, John M.; Knickerbocker, John U.; Tsang, Cornelia K., Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers.
  2. Andry, Paul S.; Cotte, John M.; Knickerbocker, John U.; Tsang, Cornelia K., Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers.
  3. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.
  4. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.
  5. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.
  6. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.
  7. Liao, Tsung-Jen, Chip package structure and manufacturing method thereof.
  8. Nechansky Helmut,ATX, Circuit board having a metal matrix composite inlay.
  9. Kelly Kimberley Anne ; Yu Roy, Column for module component.
  10. Barcley, Tina P., Electrical assemblage and method for removing heat locally generated therefrom.
  11. Chernyakov, Alexander; Heide, Patric; Heyen, Johann; Von Kerssenbrock, Thomas, Electrical component.
  12. Ishizaki,Toshio, Electronic component mounting board, electronic component module, method of manufacturing electronic component mounting board, and communications equipment.
  13. Lee, Eung-chang; Han, Seok-jae, Electronic device and semiconductor package with thermally conductive via.
  14. Anthony, Anthony A.; Anthony, William M., Energy conditioning circuit arrangement for integrated circuit.
  15. Yano Keiichi,JPX ; Asai Hironori,JPX, Heat transfer configuration for a semiconductor device.
  16. Baba, Osamu; Mimino, Yutaka; Aoki, Yoshio; Gotoh, Muneharu, High frequency semiconductor device.
  17. Nurminen,Janne; Nivala,Marko; Kivel?,Jarkko, High power light-emitting diode package and methods for making same.
  18. Kubo,Naoki, IC package with electrically conductive heat-radiating mechanism, connection structure and electronic device.
  19. Fromont Thierry,FRX, Integrated circuit IC package and a process for cooling an integrated circuit mounted in an IC package.
  20. Lee, SeongMin; Song, Sungmin; Ha, Jong-Woo, Integrated circuit package stacking system with redistribution and method of manufacture thereof.
  21. Anthony, William M.; Anthony, David; Anthony, Anthony, Internally overlapped conditioners.
  22. Kirihara, Masao; Hoshino, Kanako, LED module and lighting device using the same.
  23. Hashemi Hassan S., Leadless chip carrier design and structure.
  24. Hashemi, Hassan S., Leadless chip carrier design and structure.
  25. Megahed, Mohamed; Hashemi, Hassan S., Leadless chip carrier with embedded inductor.
  26. Hashemi, Hassan S., Leadless flip chip carrier design and structure.
  27. Song, Yong Seon; Jo, Kyoung Woo, Light emitting device package and lighting system including the same.
  28. Anthony, William M.; Anthony, David; Anthony, Anthony, Method for making internally overlapped conditioners.
  29. Ito, Sotaro; Takahashi, Michimasa; Mikado, Yukinobu, Method for manufacturing a multilayered circuit board.
  30. deRochemont, L. Pierre; Farmer, Peter H., Method of manufacture of ceramic composite wiring structures for semiconductor devices.
  31. deRochemont,L. Pierre; Farmer,Peter H., Method of manufacture of ceramic composite wiring structures for semiconductor devices.
  32. Basker, Veeraraghaven S.; Cotte, John Michael; Deligianni, Hariklia; Knickerbocker, John Ulrich; Kwietniak, Keith T., Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density.
  33. Gertiser, Kevin M.; Ripple, Richard A.; Lowry, Michael J.; Schten, Karl A.; Shearer, Ronald M.; Spall, Jim M., Multi-layer electrically isolated thermal conduction structure for a circuit board assembly.
  34. Asai Yasutomi,JPX ; Nagasaka Takashi,JPX, Multi-layered substrate.
  35. Ito, Sotaro; Takahashi, Michimasa; Mikado, Yukinobu, Multilayered printed circuit board and method for manufacturing the same.
  36. Ito, Sotaro; Takahashi, Michimasa; Mikado, Yukinobu, Multilayered printed circuit board and method for manufacturing the same.
  37. Nakamura,Satoshi, Printed wiring board having heat radiating means and method of manufacturing the same.
  38. Inoue Kazuaki,JPX ; Yamashita Hiroyuki,JPX ; Nakamura Norio,JPX ; Yoda Hiroyuki,JPX, Semiconductor device for heat discharge.
  39. Higashiguchi Yutaka,JPX ; Inagaki Mitsuo,JPX ; Kumai Toshio,JPX ; Ochiai Ryoichi,JPX ; Totani Makoto,JPX, Semiconductor device having terminals for heat radiation.
  40. Matsusue, Akihiro, Semiconductor package.
  41. Dhong Sang Hoo ; Hofstee Harm Peter ; Shapiro Michael Jay, Silicon packaging with through wafer interconnects.
  42. Gerald Miller ; William Ng ; Bernhard Schroter, Single board power supply with thermal conductors.
  43. Andrews, Peter S., Solid state light emitting apparatus with thermal management structures and methods of manufacturing.
  44. Hashemi, Hassan S.; Cote, Kevin, Structure and method for fabrication of a leadless chip carrier.
  45. Coccioli, Roberto; Megahed, Mohamed; Hashemi, Hassan S., Structure and method for fabrication of a leadless chip carrier with embedded antenna.
  46. Hashemi, Hassan S.; Cote, Kevin J., Structure and method for fabrication of a leadless multi-die carrier.
  47. Railkar, Tarak A.; Bantz, Paul D., Thermal via structures with surface features.
  48. Miller, Gerald; Ng, William; Schroter, Bernhard, Thermally conducting inductors.
  49. Higashiguchi Yutaka,JPX ; Hosogai Masao,JPX ; Otaguro Hiroyuki,JPX ; Yokemura Hitoshi,JPX ; Hida Masaharu,JPX, Wiring board with an insulating layer to prevent gap formation during etching.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트