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Logic placement using positionally asymmetrical partitioning method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0030517 (1993-03-12)
발명자 / 주소
  • Trimberger Stephen M. (San Jose CA) Chene Mon-Ren (Cupertino CA)
출원인 / 주소
  • Xilinx, Inc. (San Jose CA 02)
인용정보 피인용 횟수 : 56  인용 특허 : 0

초록 ▼

A modified partitioning method for placement of a circuit design into a programmable integrated circuit device having a specific distribution of physical resources along a horizontal or vertical line in the device. The circuit design includes a plurality of circuit elements, for example three-state

대표청구항 ▼

A partitioning method for placing a circuit design into a programmable integrated circuit device having a distribution of physical resources along a horizontal or vertical line, the circuit design comprising a plurality of circuit elements, some of which are to be distributed to said physical resour

이 특허를 인용한 특허 (56)

  1. Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with fast procedure for finding a levelizing cut point.
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  2. Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with median control and increase in resolution.
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  3. Hong Merit Y., Apparatus and method of orienting asymmetrical semiconductor devices in a circuit.
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  4. Agarwal Anant, Circuit partitioning technique for use with multiplexed inter-connections.
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  5. Trimberger Stephen M., Computer-implemented method of optimizing a time multiplexed programmable logic device.
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  6. Hochapfel, Eric G. F., Cross function block partitioning and placement of a circuit design onto reconfigurable logic devices.
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  7. Lee, Chong M., Data compression for computer-aided design systems.
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  8. Southgate Timothy J. ; Wenzler Michael, Design file templates for implementation of logic designs.
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  9. Heile Francis B., Electronic design automation tool for display of design profile.
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  10. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector clock lines.
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  11. Tse John ; Lee Fung Fung ; Mendel David Wolk, Fitting for incremental compilation of electronic designs.
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  12. Tse John ; Lee Fung Fung, Gain matrix for hierarchical circuit partitioning.
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  13. Bruce Pedersen ; Francis B. Heile ; Marwan Adel Khalaf ; David Wolk Mendel, Generation of sub-netlists for use in incremental compilation.
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  14. Pedersen Bruce ; Heile Francis B. ; Khalaf Marwan Adel ; Mendel David Wolk, Generation of sub-netlists for use in incremental compilation.
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  15. Southgate Timothy J. ; Wenzler Michael, Graphic editor for block diagram level design of circuits.
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  16. Southgate, Timothy J.; Wenzler, Michael, Graphic editor for block diagram level design of circuits.
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  17. Lee Fung Fung ; Tse John, Hierarchical circuit partitioning using sliding windows.
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  18. Heile Francis B. ; Fairbanks Brent A., Incremental compilation of electronic design for work group.
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  19. Heile Francis B. ; Rawls Tamlyn V., Interface for compiling project variations in electronic design environments.
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  20. Heile Francis B. ; Rawls Tamlyn V. ; Herrmann Alan L. ; Fairbanks Brent A. ; Karchmer David, Local compilation in context within a design hierarchy.
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  21. Southgate Timothy J., Method and apparatus for automated circuit design.
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  22. Mendel David Wolk, Method and apparatus for contemporaneously compiling an electronic circuit design by contemporaneously bipartitioning the electronic circuit design using parallel processing.
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  23. Shouen Akihisa,JPX, Method and apparatus for designing a circuit by describing logic design information with a hardware description language.
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  24. Kanazawa Yuzi,JPX, Method and apparatus for optimizing cell allocation.
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  25. Raza S. Babar, Method and apparatus to generate mask programmable device.
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  26. Raza S. Babar, Method and apparatus to generate mask programmable device.
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  27. Maamari, Fadi; Shum, Sonny Ngai San, Method and program product for detecting bus conflict and floating bus conditions in circuit designs.
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  28. Chopra,Manu; Du,Xiaoqun; Hardin,Ronald H.; Jain,Alok; Kurshan,Robert P.; Mahajan,Pratik; Prakash,Ravi; Ravi,Kavita, Method and system for partitioning an integrated circuit design.
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  29. Chopra,Manu; Du,Xiaoqun; Jain,Alok; Kurshan,Robert P.; Marschner,Franz Erich; Ravi,Kavita, Method and system for verifying circuit designs through propagation of assertions.
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  30. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
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  31. Cooke, Laurence H.; Phillips, Christopher E.; Wong, Dale, Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic.
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  32. Mohan Sundararajarao ; Trimberger Stephen M., Method for configuring FPGA memory planes for virtual hardware computation.
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  33. Southgate Timothy J., Method for providing remote software technical support.
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  34. Tadokoro Hirofumi,JPX ; Arai Kenji,JPX, Method of laying out interconnections.
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  35. Stephen M. Trimberger ; Richard A. Carberry ; Robert Anders Johnson ; Jennifer Wong, Method of time multiplexing a programmable logic device.
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  36. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
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  37. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
    상세보기
  38. Baxter Glenn A., Method to back annotate programmable logic device design files based on timing information of a target technology.
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  39. Southgate Timothy J., Methods and apparatus for simulating a portion of a circuit design.
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  40. Pedersen Bruce B., Methods for allocating circuit design portions among physical circuit portions.
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  41. Tse John (El Cerrito CA) Mendel David W. (Sunnyvale CA), Methods for partitioning circuits in order to allocate elements among multiple circuit groups.
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  42. Fotakis,Dimitris K.; Jukl,Milan F., Methods for tiling integrated circuit designs.
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  43. Klenk,Juergen; Ziegler,Patrick, Network visualization tool utilizing iterative rearrangement of nodes on a grid lattice using gradient method.
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  44. Trimberger Stephen M., Optimizing and operating a time multiplexed programmable logic device.
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  45. Kazarian Peter J., Optimizing chain placement in a programmable logic device.
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  46. Scepanovic Ranko ; Koford James S. ; Jones Edwin R. ; Kudryavtsev Valeriy B.,RUX ; Andreev Alexander E.,RUX ; Aleshin Stanislav V.,RUX ; Podkolzin Alexander S.,RUX, Physical design automation system and process for designing integrated circuit chips using generalized assignment.
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  47. Scepanovic Ranko (San Jose CA) Koford James S. (San Jose CA) Kudryavtsev Valeriy B. (Moscow RUX) Andreev Alexander E. (Moskovskaja Oblast RUX) Aleshin Stanislav V. (Moscow RUX) Podkolzin Alexander S., Physical design automation system and process for designing integrated circuit chips using multiway partitioning with co.
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  48. Grodd, Laurence W., Placement based design cells injection into an integrated circuit design.
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  49. Alpert, Charles J.; Kim, Myung-Chul; Li, Zhuo; Viswanathan, Natarajan; Ward, Samuel I., Placement of structured nets.
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  50. Chaudhary Kamal ; Nag Sudip K., Post-placement residual overlap removal method for core-based PLD programming process.
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  51. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
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  52. Mashita, Hiromitsu; Kotani, Toshiya; Maesono, Atsushi; Nakano, Ayako; Fujisawa, Tadahito, Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device.
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  53. Sundararajarao Mohan ; Stephen M. Trimberger, System and method of computation in a programmable logic device using virtual instructions.
    상세보기
  54. Ochotta Emil S., Template-based simulated annealing move-set that improves FPGA architectural feature utilization.
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  55. Arnold Ginetti FR, Updating placement during technology mapping.
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  56. Arnold Ginetti FR, Using budgeted required time during technology mapping.
    상세보기

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