이 특허를 인용한 특허 (67)

1. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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2. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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3. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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4. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.

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10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.

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11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.

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15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.

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16. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.

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17. Jacobs Eino, Computer system, cache memory and process for cache entry replacement with selective locking of elements in different ways and groups.

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18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.

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19. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.

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20. Moore, Charles Robert, Data processing system and method for fetching instruction blocks in response to a detected block sequence.

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21. Furtek, Frederick Curtis; Master, Paul L., External memory controller.

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22. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.

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23. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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24. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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25. Scheuermann,Walter James, Hardware implementation of the secure hash standard.

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26. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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27. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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28. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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29. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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30. Bak,Lars; H철lzle,Urs, Inline database for receiver types in object-oriented systems.

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31. Douglas, Jonathan P., Instruction pipe and stall therefor to accommodate shared access to return stack buffer.

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32. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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33. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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34. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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35. Naylor, Rowan Nigel, Method and apparatus for retrieving application-specific code using memory access capabilities of a host processor.

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36. Kodama Hisashi,JPX ; Araki Toshiyuki,JPX, Method and processor for changing program by replacing instruction stored in ROM with predetermined value to be interpreted as an instruction.

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37. Master, Paul L., Method and system for achieving individualized protected space in an operating system.

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38. Master, Paul L., Method and system for creating and programming an adaptive computing engine.

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39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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41. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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42. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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43. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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44. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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45. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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46. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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47. Holzle, Urs; Griesemer, Robert, Method apparatus for implementing multiple return sites.

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48. Renno, Erik K.; Strom, Oyvind; Lund, Morten W., Method for performing a return operation in parallel with setting status flags based on a return value register test.

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49. May,Christian; Freiwald,J체rgen; Brixel,Olaf, Method of protecting entry addresses.

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50. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.

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51. Stotzer, Eric J.; Granston, Elana D.; Ward, Alan S., Methods and apparatus for reducing the size of code with an exposed pipeline by encoding NOP operations as instruction operands.

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52. Brown Richard A. ; Simar Ray ; Seshan Natarajan, Multicycle NOP.

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53. Matsumoto Toshio,JPX, Priority-based memory management method and apparatus.

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54. Moore, Charles Robert, Processor and method for performing a hardware test during instruction execution in a normal mode.

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55. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.

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56. Sunayama, Ryuichi; Morita, Kuniki; Inoue, Aiichiro, Program counter control method and processor thereof for controlling simultaneous execution of a plurality of instructions including branch instructions using a branch prediction mechanism and a delay instruction for branching.

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57. Freeman Jackie Andrew, Programmable branch prediction system and method for inserting prediction operation which is independent of execution o.

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58. Niot, Francois, Reduced instruction fetch latency in a system including a pipelined processor.

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59. Okayama Sachiko,JPX ; Katsuta Hiroshi,JPX, Saving a program counter value as the return address in an arbitrary general purpose register.

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60. Master,Paul L.; Watson,John, Storage and delivery of device features.

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61. Blandy Geoffrey Owen ; Saba Maher Afif, System and method for instruction burst performance profiling for single-processor and multi-processor systems.

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62. Blandy Geoffrey Owen ; Saba Maher Afif ; Urquhart Robert John, System and method for multi-phased performance profiling of single-processor and multi-processor systems.

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63. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.

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64. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.

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65. Kiuchi Atsushi (Kunitachi JPX) Nakagawa Tetsuya (Koganei JPX), System with loop buffer and repeat control circuit having stack for storing control information.

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66. Whalley, David; Tyson, Gary, Systems, methods, and computer program products for packing instructions into register files.

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67. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.

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