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Neuro-chip and neurocomputer having the chip

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06T-001/40   
미국특허분류(USC) 395/27 ; 395/800 ; 395/20003 ; 364/DIG ; 1
출원번호 US-0285767 (1994-08-03)
우선권정보 JP-0049972 (1990-03-01)
발명자 / 주소
출원인 / 주소
인용정보 피인용 횟수 : 58  인용 특허 : 0
초록
▼

A neuro-chip comprising a plurality of neuron operation circuits, a broadcast bus terminal for supplying data in parallel to the neuron operation circuits and receiving data in parallel therefrom, a program data bus connected to the neuron operation circuits, a program data bus terminal for supplying a common program externally input, to the neuron operation circuits through the program data bus, a ring bus connecting the neuron operation circuits, and a plurality of ring bus terminals connected to the ring bus, for transferring data among the neuron ope...

대표
청구항
▼

A neuro-chip which comprises: a plurality of neuron operation circuit means, each of said neuron operation circuit means for simulating neurons, for learning, and for functioning as a neuron arranged in a plurality of layers, at least two said plurality of neuron operation circuit means being connecting neuron operation circuit means for connection with other neuron operation circuit means which are not a part of said neuro-chip; a broadcast bus connected to each of said neuron operation circuit means which broadcasts data between each of said neuron ope...

이 특허를 인용한 특허 피인용횟수: 58

  1. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2013028380884.
  2. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2015049015352.
  3. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2014048706916.
  4. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2009107606943.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2015109164952.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543795.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098533431.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
  10. Master, Paul L.; Uvacek, Bohumir. Apparatus and method for adaptive multimedia reception and transmission in communication environments. USP2015049002998.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2016059330058.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2014118880849.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2012088250339.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements. USP2017039594723.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2012078225073.
  16. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James. Communications module, device, and method for implementing a system acquisition function. USP2009117620097.
  17. Jannarone Robert. Concurrent learning and performance information processing system. USP2001096289330.
  18. Master, Paul L.; Watson, John. Configurable hardware based digital imaging apparatus. USP2009107609297.
  19. Scheuermann, W. James; Hogenauer, Eugene B.. Control node for multi-core system. USP20190110185502.
  20. Billings Roger E. (26900 E. Pink Hill Rd. Independence MO 64057-3294). Data transmission system with parallel packet delivery. USP1997115684956.
  21. Furtek, Frederick Curtis; Master, Paul L.. External memory controller. USP2012098266388.
  22. Furtek, Frederick Curtis; Master, Paul L.. External memory controller node. USP2014078769214.
  23. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077984247.
  24. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077979646.
  25. Scheuermann,Walter James. Hardware implementation of the secure hash standard. USP2009027489779.
  26. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2017059665397.
  27. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2012068200799.
  28. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2010017653710.
  29. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2014078782196.
  30. Luo, Fa-Long; Uvacek, Bohumir. IC for universal computing with near zero programming complexity. USP2005096947916.
  31. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2013058442096.
  32. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2010027668229.
  33. Sambhwani,Sharad; Heidari,Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2009037512173.
  34. Meng Wan-Yu,TWX ; Chang Cheng-Kai,TWX ; Chang Hwai-Tsu,TWX ; Hsu Fang-Ru,TWX ; Lee Ming-Rong,TWX. Method and apparatus for processing data in a neural network. USP2000036041322.
  35. Master, Paul L.. Method and system for achieving individualized protected space in an operating system. USP2010027660984.
  36. Master, Paul L.. Method and system for creating and programming an adaptive computing engine. USP2011017865847.
  37. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2015059037834.
  38. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2016079396161.
  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2013118589660.
  40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2010077752419.
  41. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2014078767804.
  42. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2012088249135.
  43. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107809050.
  44. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107822109.
  45. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn. Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information. USP2009017478031.
  46. Crouch,Simon Edwin. Network modelling. USP2007077249115.
  47. Louis, Didier; Tannhof, Pascal; Steimle, Andre. Neural chip architecture and neural networks incorporated therein. USP2003026523018.
  48. Furber,Stephen B.. Neural network component. USP2008117457787.
  49. Maruyama Masakatsu,JPX ; Nakahira Hiroyuki,JPX ; Fukuda Masaru,JPX ; Sakiyama Shiro,JPX. Neural network for voice and pattern recognition. USP2000056067536.
  50. Didier Louis FR; Pascal Tannhof FR; Andre Steimle FR. Neuron architecture having a dual structure and neural networks incorporating the same. USP2002126502083.
  51. McBride, Chad B.. Pipelined hardware implementation of a neural network circuit. USP2004126836767.
  52. Master, Paul L.. Profiling of software and circuit designs utilizing data operation analyses. USP2012098276135.
  53. Master,Paul L.; Watson,John. Storage and delivery of device features. USP2009027493375.
  54. Lee, Te-Won; Lewicki, Michael S.; Sejnowski, Terrence J.. System and method of separating signals. USP2004096799170.
  55. Master, Paul L.; Watson, John. System for adapting device standards after manufacture. USP2009107602740.
  56. Master, Paul L.; Watson, John. System for authorizing functionality in adaptable hardware devices. USP201109E042743.
  57. Katragadda, Ramana; Spoltore, Paul; Howard, Ric. Task definition for specifying resource requirements. USP2012018108656.
  58. Smith Jay L.. Trainable, state-sampled, network controller. USP1998085796922.

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