|국가/구분||United States(US) Patent 등록|
|미국특허분류(USC)||395/27 ; 395/800 ; 395/20003 ; 364/DIG ; 1|
|발명자 / 주소|
|출원인 / 주소|
|인용정보||피인용 횟수 : 58 인용 특허 : 0|
A neuro-chip comprising a plurality of neuron operation circuits, a broadcast bus terminal for supplying data in parallel to the neuron operation circuits and receiving data in parallel therefrom, a program data bus connected to the neuron operation circuits, a program data bus terminal for supplying a common program externally input, to the neuron operation circuits through the program data bus, a ring bus connecting the neuron operation circuits, and a plurality of ring bus terminals connected to the ring bus, for transferring data among the neuron ope...
A neuro-chip which comprises: a plurality of neuron operation circuit means, each of said neuron operation circuit means for simulating neurons, for learning, and for functioning as a neuron arranged in a plurality of layers, at least two said plurality of neuron operation circuit means being connecting neuron operation circuit means for connection with other neuron operation circuit means which are not a part of said neuro-chip; a broadcast bus connected to each of said neuron operation circuit means which broadcasts data between each of said neuron ope...