$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Magnetic induction coil for semiconductor devices 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/02
  • H01F-027/06
  • H01F-027/30
출원번호 US-0512260 (1995-08-07)
우선권정보 JP-0265221 (1992-10-05)
발명자 / 주소
  • Matsuzaki Kazuo (Kanagawa JPX)
출원인 / 주소
  • Fuji Electric Co., Ltd. (Kanagawa JPX 03)
인용정보 피인용 횟수 : 50  인용 특허 : 0

초록

A magnetic induction coil is mounted directly on and integrated with a semiconductor wafer containing integrated circuitry for a stable power source. Grooves are etched in the reverse face of the wafer substrate, an insulating film is applied, and conducting material fills the grooves, forming the c

대표청구항

A magnetic induction device, the elements of which are coupled to a semiconductor device, comprising: a two-faced substrate containing a semiconductor device on one face; grooves formed in a pattern of a coil on a reverse face of the substrate; an insulating film formed on said reverse face for cove

이 특허를 인용한 특허 (50)

  1. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
  2. Sapone, Giuseppina, Chip to package interface.
  3. Sapone, Giuseppina, Chip to package interface.
  4. Kie Y. Ahn ; Leonard Forbes, Coupled multilayer soft magnetic films for high frequency microtransformer for system-on-chip power supply.
  5. Tang, Yiwu; Jin, Zhang, High Q transformer disposed at least partly in a non-semiconductor substrate.
  6. Lin, Mou-Shiung, High performance IC chip having discrete decoupling capacitors attached to its IC surface.
  7. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
  8. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
  9. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  10. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  11. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  12. Lee, Jong-Hoon; Song, Young Kyu; Yoon, Jung Ho; Jow, Uei Ming; Zhang, Xiaonan; Lane, Ryan David, High quality factor filter implemented in wafer level packaging (WLP) integrated device.
  13. Song, Young K.; Park, Yunseo; Zhang, Xiaonan; Lane, Ryan D.; Nejati, Babak; Hadjichristos, Aristotele; Chen, Xiaoming, High quality factor inductor implemented in wafer level packaging (WLP).
  14. Rofougaran, Ahmadreza (Reza), Inductively coupled integrated circuit with magnetic communication path and methods for use therewith.
  15. Dang, Bing; Knickerbocker, John U.; Liu, Yang, Integrated circuit (IC) test probe.
  16. Pagani, Alberto; Girlando, Giovanni, Integrated electronic device with transceiving antenna and magnetic interconnection.
  17. Pagani, Alberto; Girlando, Giovanni, Integrated electronic device with transceiving antenna and magnetic interconnection.
  18. Pagani, Alberto; Girlando, Giovanni, Integrated electronic device with transceiving antenna and magnetic interconnection.
  19. Kahlmann, Frank; Strzalkowski, Bernhard; Werner, Wolfgang, Integrated transformer configuration.
  20. Sin, Johnny Kin-On; Peng, Lulu; Wu, Rongxiang; Sumida, Hitoshi; Toyoda, Yoshiaki; Akahane, Masashi, Isolator and isolator manufacturing method.
  21. Sin, Johnny Kin On; Peng, Lulu; Wu, Rongxiang; Sumida, Hitoshi; Toyoda, Yoshiaki; Akahane, Masashi, Isolator and method of manufacturing isolator.
  22. Joshi, Rajeev, Leadframe based magnetics package.
  23. Ravid, Shmuel; Sover, Ra′anan, Method for integrated high Q inductors in FCGBA packages.
  24. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  26. Ahn, Kie Y.; Forbes, Leonard, Microtransformer for system-on-chip power supply.
  27. Ahn, Kie Y.; Forbes, Leonard, Microtransformer for system-on-chip power supply.
  28. Ahn,Kie Y.; Forbes,Leonard, Microtransformer for system-on-chip power supply.
  29. Sin, Johnny Kin On; Wu, Rongxiang; Hui, Ron Shu Yuen, Monolithic magnetic induction device.
  30. Lowther Rex E. ; Young William R., Parasitic current barriers.
  31. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  32. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  33. Nakagawa, Tomokatsu; Chikawa, Yasunori; Rai, Akiteru; Katoh, Tatsuya; Sugiyama, Takuya, Semiconductor device and display apparatus.
  34. Anzai,Noritaka; Terui,Makoto, Semiconductor device and method for fabricating the same.
  35. Anzai,Noritaka; Terui,Makoto, Semiconductor device and method for fabricating the same.
  36. Watanabe,Hiroto; Nakayama,Osamu; Shiratsuchi,Osamu; Daido,Kazuhiko, Semiconductor device having antenna connection electrodes.
  37. Jaouen Herve,FRX ; Marty Michel,FRX, Semiconductor device having separated exchange means.
  38. Freerk Van Rijs NL; Ronald Dekker NL, Semiconductor elements for semiconductor device.
  39. Hoyt, Reed W.; Lanza, John F., System and method for short range wireless communication.
  40. Babcock,Douglas W.; Duris,Robert A.; Hecht,Bruce, T-coil apparatus and method for compensating capacitance.
  41. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  48. Kim, Jonghae; Wang, Feng; Nowak, Matthew, Transformer signal coupling for flip-chip integration.
  49. Kim, Jonghae; Wang, Feng; Nowak, Matthew M., Transformer signal coupling for flip-chip integration.
  50. Josefosky, John T; Tang, Yiwu; Hayward, Roger, Transformer within wafer test probe.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로