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Select set-based technology mapping method and apparatus 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/10
출원번호 US-0231595 (1994-04-21)
발명자 / 주소
  • Cox William D. (San Jose CA) Lehmann Eric E. (San Francisco CA) Lulla Mukesh T. (Santa Clara CA) Nathamuni Venkatesh R. (San Jose CA)
출원인 / 주소
  • QuickLogic Corporation (Santa Clara CA 02)
인용정보 피인용 횟수 : 53  인용 특허 : 0

초록 ▼

A logic circuit is implemented on a macrocell of a field programmable device using select sets of a logic function which represents a transformation of the one or more input signals of the logic circuit to the output signal of the logic circuit. Select sets of a logic function are determined (i) by

대표청구항 ▼

A method of implementing a logic circuit with one output line capable of carrying an output signal on a macrocell of a programmable gate array, comprising the steps of: determining one or more select sets of a logic function representing the output signal of said logic circuit. at least one of said

이 특허를 인용한 특허 (53)

  1. Belkhale Krishna ; Roy Sumit ; Varma Devadas, Cluster determination for circuit implementation.
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  2. Trimberger Stephen M., Computer-implemented method of optimizing a time multiplexed programmable logic device.
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  4. David E. Wallace, Digital circuit layout techniques.
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  5. Wallace,David E, Digital circuit layout techniques using binary decision diagram for identification of input equivalence.
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  6. Wallace,David E, Digital circuit layout techniques using identification of input equivalence.
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  7. Whitaker, Sterling R.; Miles, Lowell H.; Cameron, Eric G.; Donohoe, Gregory W.; Gambles, Jody W., Digital circuits using universal logic gates.
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  8. Whitaker, Sterling R.; Miles, Lowell H.; Cameron, Eric G., Digital design using selection operations.
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  9. Whitaker, Sterling R.; Miles, Lowell H.; Cameron, Eric G.; Gambles, Jody W., Digital logic optimization using selection operators.
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  10. Baeckler, Gregg William, Early logic mapper during FPGA synthesis.
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  11. Fuller Christine Marie ; Gould Scott Whitney ; Hartman Steven Paul ; Millham Eric Ernest ; Yasar Gulsun, Field programmable gate arrays using semi-hard multicell macros.
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  12. Ling Zhang Qiao,SGX ; Zhen Cai,SGX, Hybrid design method and apparatus for computer-aided circuit design.
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  13. Whitaker, Sterling R.; Miles, Lowell H., Integrated circuit cell library.
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  14. Oota Hiroshi,JPX, Layout apparatus for LSI using cell library and method therefor.
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  15. Singh Virinder ; Liang Mike, Method and apparatus for netlist filtering and cell placement.
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  16. Teig, Steven; Hetzel, Asmus, Method and apparatus for performing technology mapping.
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  17. Teig, Steven; Hetzel, Asmus, Method and apparatus for performing technology mapping.
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  18. Teig, Steven; Hetzel, Asmus, Method and apparatus for performing technology mapping.
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  19. Teig,Steven; Hetzel,Asmus, Method and apparatus for performing technology mapping.
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  20. Teig, Steven; Hetzel, Asmus, Method and apparatus for pre-tabulating sub-networks.
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  21. Teig,Steven; Hetzel,Asmus, Method and apparatus for pre-tabulating sub-networks.
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  22. Teig,Steven; Hetzel,Asmus, Method and apparatus for pre-tabulating sub-networks.
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  23. Teig, Steven; Hetzel, Asmus, Method and apparatus for producing a circuit description of a design.
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  24. Teig, Steven; Hetzel, Asmus, Method and apparatus for producing a circuit description of a design.
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  25. Teig,Steven; Hetzel,Asmus, Method and apparatus for specifying encoded sub-networks.
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  26. Teig,Steven; Hetzel,Asmus, Method and apparatus for specifying encoded sub-networks.
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  27. Teig, Steven; Hetzel, Asmus, Method and apparatus replacing sub-networks within an IC design.
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  28. Mohan Sundararajarao ; Trimberger Stephen M., Method for configuring FPGA memory planes for virtual hardware computation.
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  29. Baeckler, Gregg William, Method for early logic mapping during FPGA synthesis.
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  30. Kaviani Alireza S.,CAX, Method for implementing a programmable logic device having look-up table and product-term circuitry.
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  31. Masamichi Kawarabayashi JP; Takuo Nakaki JP, Method of changing logic circuit portion into gated clock portion and recording medium storing a program for carrying out the method.
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  32. Stephen M. Trimberger ; Richard A. Carberry ; Robert Anders Johnson ; Jennifer Wong, Method of time multiplexing a programmable logic device.
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  33. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
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  34. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
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  35. Bergamaschi,Reinaldo A.; Bhattacharya,Subhrajit, Methods and arrangements for automatically interconnecting cores in systems-on-chip.
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  36. Whitaker,Sterling R.; Miles,Lowell H., Optimization of digital designs.
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  37. Trimberger Stephen M., Optimizing and operating a time multiplexed programmable logic device.
    상세보기
  38. Maki, Gary K.; Bhatia, Prakash R., Pass-transistor very large scale integration.
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  39. Allen Ernest, Process for programming PLDs and embedded non-volatile memories.
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  40. Ang, Roger; Ahuja, Atul; Lulla, Mukesh T.; Borkovic, Drazen; Small, Brian D.; Tralka, Charles C.; Chan, Andrew K.; Yee, Kevin K., Programmable device with an embedded portion for receiving a standard circuit design.
    상세보기
  41. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
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  42. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
    상세보기
  43. Lakshmi Narasimha Reddy ; Thomas Edward Rosser, Pseudo-anding in dynamic logic circuits.
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  44. Sueyoshi, Toshinori; Iida, Masahiro; Amagasaki, Motoki; Taketa, Kazuhiko; Heishi, Taketo; Suzuki, Nobuharu, Reconfigurable logic block, programmable logic device provided with the reconfigurable logic block, and method of fabricating the reconfigurable logic block.
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  45. Cox William D., Reducing propagation delays in a programmable device.
    상세보기
  46. Teig,Steven; Hetzel,Asmus, Structure for storing a plurality of sub-networks.
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  47. Lakshmi Narasimha Reddy ; Thomas Edward Rosser, System and method for restructuring of logic circuitry.
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  48. Reddy Lakshmi Narasimha ; Rosser Thomas Edward, System and method for restructuring of logic circuitry.
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  49. Sundararajarao Mohan ; Stephen M. Trimberger, System and method of computation in a programmable logic device using virtual instructions.
    상세보기
  50. Arnold Ginetti FR, Updating placement during technology mapping.
    상세보기
  51. Arnold Ginetti FR, Using budgeted required time during technology mapping.
    상세보기
  52. Mahajan Shekhar Y. ; Shao Wenyi, Virtual programmable device and method of programming.
    상세보기
  53. Carreira,Alexander; Vogenthaler,Alexander R., Visualizing hardware cost in high level modeling systems.
    상세보기

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