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Direct stacked and flip chip power semiconductor device structures 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
  • H01L-023/48
  • H05K-007/20
출원번호 US-0316996 (1994-10-03)
발명자 / 주소
  • Fillion Raymond A. (Niskayuna NY) Wildi Eric J. (Niskayuna NY) Korman Charles S. (Schenectady NY) El-Hamamsy Sayed-Amr (Schenectady NY) Gasworth Steven M. (Glenville NY) DeVre Michael W. (Scotia NY)
출원인 / 주소
  • General Electric Company (Schenectady NY 02)
인용정보 피인용 횟수 : 175  인용 특허 : 0

초록 ▼

Power semiconductor device structures and assemblies with improved heat dissipation characteristics and low impedance interconnections include a thermally-conductive dielectric layer, such as diamondlike carbon (DLC) overlying at least portions of the active major surface of a semiconductor chip, wi

대표청구항 ▼

A stacked power semiconductor device configuration comprising: first and second power semiconductor device structures, each of said power semiconductor device structures comprising: a semiconductor chip having an active major surface and an opposite major surface, contact pads on the active major su

이 특허를 인용한 특허 (175)

  1. Kaskoun, Kenneth; Gu, Shiqun; Nowak, Matthew, 3-D integrated circuit lateral heat dissipation.
    상세보기
  2. Pierson Mark V. ; Spink ; Jr. Kenneth L. ; Youngs ; Jr. Thurston B., Advanced chip packaging structure for memory card applications.
    상세보기
  3. Larking, John E., Arrangement for high frequency application.
    상세보기
  4. Topfer Manfred,DEX ; Kaulfersch Eberhard,DEX ; Weib Stefan,DEX ; Reichl Herbert,DEX, Chip arrangement and method of producing the same.
    상세보기
  5. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
    상세보기
  6. Surridge Robert,CAX, Chip mounting scheme.
    상세보기
  7. Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Li-Ren; Lo, Hsin-Jung, Chip package and method for fabricating the same.
    상세보기
  8. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
    상세보기
  9. Standing,Martin; Schofield,Hazel D, Chip scale surface mounted device and process of manufacture.
    상세보기
  10. Standing,Martin; Schofield,Hazel Deborah, Chip scale surface mounted device and process of manufacture.
    상세보기
  11. Standing,Martin; Schofield,Hazel Deborah, Chip scale surface mounted device and process of manufacture.
    상세보기
  12. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
    상세보기
  13. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
    상세보기
  14. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang; Lo, Hsin-Jung, Chip structure.
    상세보기
  15. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
    상세보기
  16. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
    상세보기
  17. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
    상세보기
  18. Farlow, Andy; Pavier, Mark; Sawle, Andrew N.; Pearson, George; Standing, Martin, Chip-scale package.
    상세보기
  19. Standing, Martin; Clarke, Robert J, Chip-scale package.
    상세보기
  20. McConnelee, Paul Alan; Gowda, Arun Virupaksha; Burke, Elizabeth Ann; Durocher, Kevin Matthew, Component protection for advanced packaging applications.
    상세보기
  21. Ewe, Henrik; Mahler, Joachim, Component, power component, apparatus, method of manufacturing a component, and method of manufacturing a power semiconductor component.
    상세보기
  22. Standing, Martin; Clarke, Robert J, Conductive chip-scale package.
    상세보기
  23. Shi, Lei; Liu, Kai; Sun, Ming, Conductive clip for semiconductor device package.
    상세보기
  24. Ball Michael B., Conductive lines on the back side of wafers and dice for semiconductor interconnects.
    상세보기
  25. Krishnan, Shutesh; Wang, Soon Wei, Connector assembly and method of manufacture.
    상세보기
  26. Kraig J. Olejniczak ; Keith C. Burgers ; Simon S. Ang ; Errol V Porter, Conversion of electrical energy from one form to another, and its management through multichip module structures.
    상세보기
  27. Larking,John E., Direct FET device for high frequency application.
    상세보기
  28. Larking,John E., Direct fet device for high frequency application.
    상세보기
  29. Fritsch,Ingrid; Beitle, Jr.,Robert; Aguilar,Zoraida, Electrochemical method for detecting water born pathogens.
    상세보기
  30. Otremba, Ralf, Electronic module with switching functions and method for producing the same.
    상세보기
  31. Triantafyllou, Markos; Specks, Will; Escoffre, Claude, Electronic package assembly.
    상세보기
  32. Joshi Rajeev, High performance flip chip package.
    상세보기
  33. Joshi Rajeev, High performance flip chip package.
    상세보기
  34. Joshi, Rajeev, High performance multi-chip flip chip package.
    상세보기
  35. Joshi,Rajeev, High performance multi-chip flip chip package.
    상세보기
  36. Rajeev Joshi, High performance multi-chip flip chip package.
    상세보기
  37. Joshi, Rajeev, High performance multi-chip flip package.
    상세보기
  38. Boulay, Jean Marie; Ghannam, Ayad, High power semiconductor device for wireless applications and method of forming a high power semiconductor device.
    상세보기
  39. Standing,Martin, High voltage semiconductor device housing with increased clearance between housing can and die for improved flux flushing.
    상세보기
  40. Lin, Heny; Zhang, Jason; Guerra, Alberto, III-nitride transistor stacked with FET in a package.
    상세보기
  41. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
    상세보기
  42. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
    상세보기
  43. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
    상세보기
  44. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
    상세보기
  45. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
    상세보기
  46. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
    상세보기
  47. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
    상세보기
  48. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
    상세보기
  49. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
    상세보기
  50. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
    상세보기
  51. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
    상세보기
  52. Fillion Raymond Albert ; Burdick ; Jr. William Edward ; Kolc Ronald Frank ; Rose James Wilson ; Claydon Glenn Scott, Integrated circuit package including window frame.
    상세보기
  53. Gabara,Thaddeus John, Integrated circuit with stacked-die configuration utilizing substrate conduction.
    상세보기
  54. Myers, Bruce A.; Brauer, Eric A., Liquid cooled power electronic circuit comprising a stacked array of directly cooled semiconductor chips.
    상세보기
  55. Izak Bencuya ; Maria Christina B. Estacio PH; Steven P. Sapp ; Consuelo N. Tangpuz PH; Gilmore S. Baje PH; Rey D. Maligro PH, Low Resistance package for semiconductor devices.
    상세보기
  56. Kajiwara, Ryoichi; Koizumi, Masahiro; Morita, Toshiaki; Takahashi, Kazuya; Kishimoto, Munehisa; Ishii, Shigeru; Hirashima, Toshinori; Takahashi, Yasushi; Hata, Toshiyuki; Sato, Hiroshi; Ookawa, Keiichi, MOSFET package.
    상세보기
  57. Kajiwara,Ryoichi; Koizumi,Masahiro; Morita,Toshiaki; Takahashi,Kazuya; Kishimoto,Munehisa; Ishii,Shigeru; Hirashima,Toshinori; Takahashi,Yasushi; Hata,Toshiyuki; Sato,Hiroshi; Ookawa,Keiichi, MOSFET package.
    상세보기
  58. Kajiwara,Ryoichi; Koizumi,Masahiro; Morita,Toshiaki; Takahashi,Kazuya; Kishimoto,Munehisa; Ishii,Shigeru; Hirashima,Toshinori; Takahashi,Yasushi; Hata,Toshiyuki; Sato,Hiroshi; Ookawa,Keiichi, MOSFET package.
    상세보기
  59. Kajiwara,Ryoichi; Koizumi,Masahiro; Morita,Toshiaki; Takahashi,Kazuya; Kishimoto,Munehisa; Ishii,Shigeru; Hirashima,Toshinori; Takahashi,Yasushi; Hata,Toshiyuki; Sato,Hiroshi; Ookawa,Keiichi, MOSFET package.
    상세보기
  60. Kajiwara,Ryoichi; Koizumi,Masahiro; Morita,Toshiaki; Takahashi,Kazuya; Kishimoto,Munehisa; Ishii,Shigeru; Hirashima,Toshinori; Takahashi,Yasushi; Hata,Toshiyuki; Sato,Hiroshi; Ookawa,Keiichi, MOSFET package.
    상세보기
  61. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
    상세보기
  62. Asai, Yasutomi; Ishino, Hiroshi, Method for manufacturing semiconductor device including semiconductor elements with electrode formed thereon.
    상세보기
  63. Lorenz, Leo; Kaindl, Michael; Schwarzbauer, Herbert; Munzing, Gerhard; Stern, Peter; Bruckmann, Manfred, Method for producing a microelectronic component of sandwich construction.
    상세보기
  64. Bowman Wayne C. ; Chen Shiaw-Jong Steve, Method of mounting a power semiconductor die on a substrate.
    상세보기
  65. Petrarca Kevin Shawn ; Knickerbocker Sarah ; Liu Joyce C. ; Mih Rebecca D., Method of producing heat dissipating structure for semiconductor devices.
    상세보기
  66. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  67. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  68. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  69. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  70. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  71. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  72. Krabe, Detlef Bernd; Weigert, Martin, Methods for performing embedded wafer-level packaging (eWLP) and eWLP devices, packages and assemblies made by the methods.
    상세보기
  73. Krabe, Detlef Bernd; Wittl, Josef, Methods for performing extended wafer-level packaging (eWLP) and eWLP devices made by the methods.
    상세보기
  74. Krabe, Detlef Bernd; Wittl, Josef, Methods for performing extended wafer-level packaging (eWLP) and eWLP devices made by the methods.
    상세보기
  75. Fallon Kenneth Michael ; Ma William Hsioh-Lien, Microelectronic package and fabrication thereof.
    상세보기
  76. Fritsch,Ingrid; Henry,Charles Sherman; Bowen,Benjamin P.; Vandaveer,Walter; Bratcher,Nicole, Microfabricated recessed disk microelectrodes: characterization in static and convective solutions.
    상세보기
  77. Fritsch, Ingrid; Beittle, Jr., Robert, Microvolume immunoabsorbant assays with amplified electrochemical detection.
    상세보기
  78. Kajiwara, Ryoichi; Koizumi, Masahiro; Morita, Toshiak; Takahashi, Kazuya; Kishimoto, Munehisa; Ishii, Shigeru; Hirashima, Toshinori; Takahashi, Yasushi; Hata, Toshiyuki; Sato, Hiroshi; Ookawa, Keiichi, Mosfet package.
    상세보기
  79. Kajiwara, Ryoichi; Koizumi, Masahiro; Morita, Toshiaki; Takahashi, Kazuya; Kishimoto, Munehisa; Ishii, Shigeru; Hirashima, Toshinori; Takahashi, Yasushi; Hata, Toshiyuki; Sato, Hiroshi; Ookawa, Keiichi, Mosfet package.
    상세보기
  80. Wheeler, Nicolas J.; Rutter, Philip, Multi-chip module semiconductor devices.
    상세보기
  81. Carney, Francis J.; Celaya, Phillip; Fauty, Joseph K.; Letterman, James P.; St. Germain, Stephen; Yoder, Jay A., Multi-chip semiconductor connector.
    상세보기
  82. Carney,Francis J.; Celaya,Phillip; Fauty,Joseph K.; Letterman,James P.; Germain,Stephen St.; Yoder,Jay A., Multi-chip semiconductor connector assemblies.
    상세보기
  83. Carney,Francis J.; Celaya,Phillip; Fauty,Joseph K.; Letterman,James P.; St. Germain,Stephen; Yoder,Jay A., Multi-chip semiconductor connector assemblies.
    상세보기
  84. Fritsch,Ingrid; Henry,Charles Sherman; Bowen,Benjamin P.; Vandaveer,Walter R.; Bratcher,Nicole, Multilayer microcavity devices and methods.
    상세보기
  85. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
    상세보기
  86. Krabe, Detlef B, Optoelectronic assembly incorporating an optical fiber alignment structure.
    상세보기
  87. Bowman Wayne C. ; Chen Shiaw-Jong Stee, Package for a power semiconductor die and power supply employing the same.
    상세보기
  88. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
    상세보기
  89. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
    상세보기
  90. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
    상세보기
  91. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
    상세보기
  92. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
    상세보기
  93. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
    상세보기
  94. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
    상세보기
  95. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
    상세보기
  96. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  97. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  98. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  99. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
    상세보기
  100. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
    상세보기
  101. Lasky, Jerome B.; Nowak, Edward J.; Sprogis, Edmund J., Power distribution design method for stacked flip-chip packages.
    상세보기
  102. Lasky, Jerome B.; Nowak, Edward J.; Sprogis, Edmund J., Power distribution design method for stacked flip-chip packages.
    상세보기
  103. Mermet-Guyennet Michel,FRX, Power electronic device.
    상세보기
  104. Burhan Ozmat ; Mustansir Hussainy Kheraluwala ; Eladio Clemente Delgado ; Charles Steven Korman ; Paul Alan McConnelee, Power electronic module packaging.
    상세보기
  105. Ozmat Burhan ; Kheraluwala Mustansir Hussainy ; Delgado Eladio Clemente ; Korman Charles Steven ; McConnelee Paul Alan, Power electronic module packaging.
    상세보기
  106. Eckardt,Dieter; Rebbereh,Carsten, Power module.
    상세보기
  107. Hanada, Toshio, Power module semiconductor device and inverter equipment, and fabrication method of the power module semiconductor device, and metallic mold.
    상세보기
  108. Fillion Raymond Albert ; Whitmore Barry Scott ; Korman Charles Steven ; Esser Albert Andreas Maria, Power overlay chip scale packages for discrete power devices.
    상세보기
  109. Lenz Michael,DEX, Power semiconductor component.
    상세보기
  110. Hosseini, Khalil; Koenigsberger, Alexander; Otremba, Ralf; Mahler, Joachim; Schloegel, Xaver; Schiess, Klaus, Power semiconductor component stack using lead technology with surface-mountable external contacts and a method for producing the same.
    상세보기
  111. Otremba, Ralf; Schloegel, Xaver, Power semiconductor component with semiconductor chip stack in a bridge circuit and method for producing the same.
    상세보기
  112. Otremba, Ralf, Power semiconductor device and method for producing it.
    상세보기
  113. Otremba, Ralf; Strack, Helmut, Power semiconductor device connected in distinct layers of plastic.
    상세보기
  114. Ewe, Henrik; Hoeglauer, Josef; Huber, Erwin; Otremba, Ralf, Power semiconductor device having lines within a housing.
    상세보기
  115. Kawanami, Yasuhiko; Isobe, Tasuku, Power semiconductor module.
    상세보기
  116. Fillion, Raymond Albert; Beaupre, Richard Alfred; Elasser, Ahmed; Wojnarowski, Robert John; Korman, Charles Steven, Power semiconductor packaging method and structure.
    상세보기
  117. Fillion,Raymond Albert; Beaupre,Richard Alfred; Elasser,Ahmed; Wojnarowski,Robert John; Korman,Charles Steven, Power semiconductor packaging method and structure.
    상세보기
  118. Standing, Martin, Process of fabricating a semiconductor package.
    상세보기
  119. Baliga, Bantval Jayant, Radio frequency (RF) power devices having faraday shield layers therein.
    상세보기
  120. Fritsch,Ingrid; Beitle, Jr.,Robert; Aguilar,Zoraida, Self-contained microelectrochemical bioassay platforms and methods.
    상세보기
  121. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
    상세보기
  122. Lin, Mou-Shiung; Yen, Huei-Mei; Lo, Hsin-Jung; Chou, Chiu-Ming; Chen, Ke-Hung, Semiconductor chip with a bonding pad having contact and test areas.
    상세보기
  123. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
    상세보기
  124. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
    상세보기
  125. Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Ching-San; Lin, Mou-Shiung, Semiconductor chip with passivation layer comprising metal interconnect and contact pads.
    상세보기
  126. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
    상세보기
  127. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
    상세보기
  128. Krishnan, Shutesh; Wang, Soon Wei, Semiconductor component and method of manufacture.
    상세보기
  129. Kajiwara, Ryoichi; Koizumi, Masahiro; Morita, Toshiaki; Takahashi, Kazuya; Kishimoto, Munehisa; Ishii, Shigeru; Hirashima, Toshinori; Takahashi, Yasushi; Hata, Toshiyuki; Sato, Hiroshi; Ookawa, Keiic, Semiconductor device.
    상세보기
  130. Kajiwara, Ryoichi; Koizumi, Masahiro; Morita, Toshiaki; Takahashi, Kazuya; Kishimoto, Munehisa; Ishii, Shigeru; Hirashima, Toshinori; Takahashi, Yasushi; Hata, Toshiyuki; Sato, Hiroshi; Ookawa, Keiichi, Semiconductor device.
    상세보기
  131. Kanazawa, Masaki, Semiconductor device.
    상세보기
  132. Mahler, Joachim; Ewe, Henrik; Mengel, Manfred, Semiconductor device.
    상세보기
  133. Okumura, Keiji; Otsuka, Takukazu; Saito, Masao, Semiconductor device.
    상세보기
  134. Okumura, Keiji; Otsuka, Takukazu; Saito, Masao, Semiconductor device.
    상세보기
  135. Okumura, Keiji; Otsuka, Takukazu; Saito, Masao, Semiconductor device.
    상세보기
  136. Okumura, Keiji; Otsuka, Takukazu; Saito, Masao, Semiconductor device.
    상세보기
  137. Oyamada, Seisei, Semiconductor device having an inner power supply plate structure.
    상세보기
  138. Standing, Martin, Semiconductor device having clips for connecting to external elements.
    상세보기
  139. Cardwell, Charles S., Semiconductor device package with improved cooling.
    상세보기
  140. Fuchs, Sven; Pavier, Mark, Semiconductor device with reduced contact resistance.
    상세보기
  141. Fuchs, Sven; Pavier, Mark, Semiconductor device with reduced contact resistance.
    상세보기
  142. Otremba, Ralf, Semiconductor module with a power semiconductor chip and a passive component and method for producing the same.
    상세보기
  143. Otremba, Ralf, Semiconductor module with a semiconductor chip and a passive component and method for producing the same.
    상세보기
  144. Otremba, Ralf, Semiconductor module with semiconductor chips and method for producing it.
    상세보기
  145. Hu,Kunzhong; Cheah,Chuan, Semiconductor package.
    상세보기
  146. Standing,Martin, Semiconductor package.
    상세보기
  147. Montgomery, Robert, Semiconductor package that includes stacked semiconductor die.
    상세보기
  148. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
    상세보기
  149. Andrus Lance ; Fraivillig James ; Barrett Edward ; High Brian, Solderable structures.
    상세보기
  150. Hauenstein, Henning M., Stacked half-bridge power module.
    상세보기
  151. Boteler, Lauren M.; Urciuoli, Damian P., Stacked power module with integrated thermal management.
    상세보기
  152. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.
    상세보기
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    상세보기
  154. Standing, Martin; Sawle, Andrew Neil, Surface mounted package with die bottom spaced from support board.
    상세보기
  155. Standing,Martin; Sawle,Andrew N, Surface mounted package with die bottom spaced from support board.
    상세보기
  156. Bach, Heinz-Gunter; Moehrle, Martin; Przyrembel, Georges, Terminating impedance circuit for an electroabsorption modulator.
    상세보기
  157. Kuo Yue, Thin film transistor with carbonaceous gate dielectric.
    상세보기
  158. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  159. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  160. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  161. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  162. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  163. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  164. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
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    상세보기
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    상세보기
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    상세보기
  168. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
    상세보기
  169. Schunk, Nikolaus W., Two-sided-access extended wafer-level ball grid array (eWLB) package, assembly and method.
    상세보기
  170. Sambhwani, Sharad Deepak; Yavuz, Mehmet, Uplink power headroom definition for E-DCH in CELL_FACH.
    상세보기
  171. Sambhwani, Sharad Deepak; Yavuz, Mehmet, Uplink power headroom definition for E-DCH in CELL—FACH.
    상세보기
  172. Ball Michael B., Use of conductive lines on the back side of wafers and dice for semiconductor interconnects.
    상세보기
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    상세보기
  174. Standing, Martin, Wafer level underfill and interconnect process.
    상세보기
  175. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
    상세보기

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