초록 ▼

A gate driver circuit includes a timing circuit, an anti-Miller surge protection circuit, and charging and discharging circuits for driving an output transistor, such as an IGBT. The anti-Miller surge protection circuit prevents the output transistor from being accidentally turned on. The gate drive

A gate driver circuit includes a timing circuit, an anti-Miller surge protection circuit, and charging and discharging circuits for driving an output transistor, such as an IGBT. The anti-Miller surge protection circuit prevents the output transistor from being accidentally turned on. The gate driver circuit provides a high impedance input, so as to allow such a gate driver circuit to be driven by a relatively smaller isolation transformer. Further, the timing circuit in the gate driver circuit of the present invention allows such isolation transformer a relative lower frequency of operation. In one embodiment, the capacitance of the output transistor\s gate terminal is used to determine the time constant of the timing circuit.

대표청구항 ▼

A driver circuit for driving a control terminal of an output transistor, said output transistor being in a conducting state when said control terminal is at a first voltage level and in a non-conducting state when said control terminal is at a second voltage level, said driver circuit receiving a co

A driver circuit for driving a control terminal of an output transistor, said output transistor being in a conducting state when said control terminal is at a first voltage level and in a non-conducting state when said control terminal is at a second voltage level, said driver circuit receiving a control signal having an active phase and an inactive phase, said driver circuit comprising: a charging circuit receiving said control signal for driving said control terminal to said first voltage level during said active phase of said control signal; a surge-protection circuit, coupled to said charging circuit and said control terminal, for preventing a surge in voltage in said control terminal that occurs at other than the active phase, said surge protection circuit being disabled during said active phase of said control signal to allow normal operation; and a discharging circuit, receiving said control signal and coupled to said control terminal, for driving said control terminal to said second voltage level following a predetermined delay, during said inactive phase of said control signal.