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Virtual processor module including a reconfigurable programmable matrix 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/00
출원번호 US-0175303 (1993-12-29)
발명자 / 주소
  • Kolchinsky Alexander (48 Gray Rd. Andover MA 01810)
인용정보 피인용 횟수 : 152  인용 특허 : 0

초록 ▼

A virtual processor has a reconfigurable, programmable logic matrix array for processing data in accord with a hardware encoded algorithm, a memory for storing a plurality of hardware configuration files for the programmable logic matrix array, each configuration file for programming an algorithm to

대표청구항 ▼

A Virtual Processor Module comprising the following components: a reconfigurable, programmable logic matrix array for processing data in accord with a hardware encoded algorithm; a memory for storing a plurality of hardware configuration files for the programmable logic matrix array, each configurat

이 특허를 인용한 특허 (152)

  1. Kurts,Tsvika; Wayner,Zelig; Bojan,Tommy, Apparatus and method for bus signal termination compensation during detected quiet cycle.
    상세보기
  2. Wright Adam, Apparatus and method for generating configuration and test files for programmable logic devices.
    상세보기
  3. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
    상세보기
  4. Hertweck, Jens, Business application inspection and modification.
    상세보기
  5. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
    상세보기
  6. Sharrit Paul ; Campini Edoardo ; Cornils Curtis L., Communicator having reconfigurable resources.
    상세보기
  7. Te'eni,Moddy; Shufer,Ilan, Component upgrading with dependency conflict resolution, knowledge based and rules.
    상세보기
  8. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
    상세보기
  9. Grinshpun, Ed; Cilli, Bruce, Configuration file framework to support high availability schema based upon asynchronous checkpointing.
    상세보기
  10. Gonzalez, Ricardo E.; Rudell, Richard L.; Ghosh, Abhijit; Wang, Albert R., Configuring a multi-processor system.
    상세보기
  11. Alfke, Peter H.; McMillan, Scott P.; Blodget, Brandon J.; Levi, Delon, Controller arrangement for partial reconfiguration of a programmable logic device.
    상세보기
  12. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  13. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  14. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  15. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
    상세보기
  16. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
    상세보기
  17. Vorbach, Martin, Data processing system.
    상세보기
  18. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
    상세보기
  19. Tsunoda, Takanobu; Atwood, Bryan; Takada, Masashi; Tanaka, Hiroshi, Data processor with internal memory structure for processing stream data.
    상세보기
  20. Williams,Kenneth M; Wang,Albert, Defining instruction extensions in a standard programming language.
    상세보기
  21. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
    상세보기
  22. Brightman,Thomas B.; Brown,Andrew T.; Brown,John F.; Farrell,James A.; Funk,Andrew D.; Husak,David J.; McLellan,Edward J.; Sankey,Mark A.; Schmitt,Paul; Priore,Donald A., Digital communications processor.
    상세보기
  23. Anderson, James Bryan, Direct memory access-based multi-processor array.
    상세보기
  24. Vorbach Martin Andreas,DEX ; Munch Robert Markus,DEX, Dynamically reconfigurable data processing system.
    상세보기
  25. Roussakov Vladimir P.,RUX, Dynamically reconfigurable distributed integrated circuit processor and method.
    상세보기
  26. Martel Sylvain ; Lafontaine Serge R. ; Hunter Ian W., Dynamically reconfigurable hardware system for real-time control of processes.
    상세보기
  27. Johnson, Scott D., Extension adapter.
    상세보기
  28. Southgate Timothy James, FPGA based configurable CPU additionally including second programmable section for implementation of custom hardware su.
    상세보기
  29. Cloutier Jocelyn, FPGA-based processor.
    상세보기
  30. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
    상세보기
  31. Brightman, Thomas B.; Funk, Andrew D.; Husak, David J.; McLellan, Edward J.; Brown, Andrew T.; Brown, John F.; Farrell, James A.; Priore, Donald A.; Sankey, Mark A.; Schmitt, Paul, High speed and high throughput digital communications processor with efficient cooperation between programmable processing components.
    상세보기
  32. Martin Vorbach DE; Robert Munch DE, I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures.
    상세보기
  33. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
    상세보기
  34. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
    상세보기
  35. Vorbach,Martin; M��nch,Robert, I/O and memory bus system for DFPS and units with two-or multi-dimensional programmable cell architectures.
    상세보기
  36. Vorbach Martin,DEX ; Munch Robert,DEX, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.
    상세보기
  37. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.
    상세보기
  38. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.
    상세보기
  39. Vorbach,Martin; M？nch,Robert, I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures.
    상세보기
  40. Williams,Kenneth Mark; Johnson,Scott Daniel; McNamara,Bruce Saylors; Wang,Albert RenRui, Instruction set for efficient bit stream and byte stream I/O.
    상세보기
  41. Trimberger,Stephen M., Integrated circuit with supervisory control circuit.
    상세보기
  42. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Integrated processor and programmable data path chip for reconfigurable computing.
    상세보기
  43. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
    상세보기
  44. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
    상세보기
  45. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
    상세보기
  46. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  47. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  48. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  49. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
    상세보기
  50. Gonzalez,Ricardo E.; Johnson,Scott; Taylor,Derek, Long instruction word processing with instruction extensions.
    상세보기
  51. Stakutis,Christopher J.; Stearns,Kevin M., Low overhead methods and apparatus for shared access storage devices.
    상세보기
  52. Stakutis,Christopher J.; Stearns,Kevin M., Low overhead methods and apparatus shared access storage devices.
    상세보기
  53. Ware, Frederick A.; Vogelsang, Thomas, Memory component having internal read modify-write operation.
    상세보기
  54. Ware, Frederick A.; Vogelsang, Thomas, Memory component having internal read-modify-write operation.
    상세보기
  55. Baxter,Michael A., Meta-address architecture for parallel, dynamically reconfigurable computing.
    상세보기
  56. Goffinet Kevin Patrick ; Rafferty ; Jr. Francis Darrell ; Songer Gail Marie ; Webb James Francis ; Wedinger Jeffrey Keith ; Young Lloyd Phillip, Method and apparatus for configuring the physical setup of multiple printers on a network.
    상세보기
  57. Groll,Franz; B？umer,J？rgen, Method and apparatus for controlling a plant.
    상세보기
  58. Burke, David, Method and apparatus for executing standard functions in a computer system using a field programmable gate array.
    상세보기
  59. Stakutis, Christopher J.; Stearns, Kevin M., Method and apparatus for high-speed access to and sharing of storage devices on a networked digital data processing system.
    상세보기
  60. Garey, Kenneth E., Method and apparatus of selecting one of a plurality of predetermined configurations using only necessary bus widths based on power consumption analysis for programmable logic device.
    상세보기
  61. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
    상세보기
  62. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
    상세보기
  63. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
    상세보기
  64. Vorbach, Martin, Method for debugging reconfigurable architectures.
    상세보기
  65. Vorbach, Martin, Method for debugging reconfigurable architectures.
    상세보기
  66. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
    상세보기
  67. Vorbach,Martin, Method for debugging reconfigurable architectures.
    상세보기
  68. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.
    상세보기
  69. Panwar Ramesh ; Hetherington Ricky C., Method for dynamically reconfiguring a processor.
    상세보기
  70. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.
    상세보기
  71. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
    상세보기
  72. Smith,Stephen J; Southgate,Timothy J, Method for managing resources in a reconfigurable computer having programmable logic resources where automatically swapping configuration data between a secondary storage device and the programmable .
    상세보기
  73. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
    상세보기
  74. Te'eni, Moddy; Shufer, Ilan, Method for resolving dependency conflicts among multiple operative entities within a computing environment.
    상세보기
  75. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.
    상세보기
  76. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
    상세보기
  77. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
    상세보기
  78. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).
    상세보기
  79. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
    상세보기
  80. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
    상세보기
  81. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  82. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  83. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  84. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  85. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  86. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  87. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
    상세보기
  88. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
    상세보기
  89. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.
    상세보기
  90. Stakutis,Christopher J.; Stearns,Kevin M., Methods and apparatus for high-speed access to and sharing of storage devices on a networked digital data processing system.
    상세보기
  91. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  92. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  93. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  94. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
    상세보기
  95. Vorbach, Martin, Methods and devices for treating and/or processing data.
    상세보기
  96. Barnett Philip C.,GBX, Microcontroller incorporating an enhanced peripheral controller for automatic updating the configuration date of multiple peripherals by using a ferroelectric memory array.
    상세보기
  97. Dao Tuan Q ; Ng Pius ; Look Paul, Modular and scalable system for signal and multimedia processing.
    상세보기
  98. Jacobson,Neil G., Network based diagnostic system and method for programmable hardware.
    상세보기
  99. Jacobson,Neil G., Network based diagnostic system and method for software reconfigurable systems.
    상세보기
  100. Robinson, Jeffrey I., Object oriented processor arrays.
    상세보기
  101. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
    상세보기
  102. Ringseth, Paul F.; Molloy, Rick; Gustafsson, Niklas; Callahan, David, Persistent local storage for processor resources.
    상세보기
  103. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
    상세보기
  104. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
    상세보기
  105. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.
    상세보기
  106. Vorbach Martin,DEX ; Munch Robert,DEX, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like).
    상세보기
  107. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
    상세보기
  108. Martin Vorbach DE; Robert Munch DE, Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like).
    상세보기
  109. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
    상세보기
  110. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
    상세보기
  111. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
    상세보기
  112. Chow, Jacky S.; Leung, Pak Hei Matthew; Tang, Eugene Yuk-Yin, Programmable architecture for digital communication systems that support vector processing and the associated methodology.
    상세보기
  113. Arnold, Jeffrey Mark; Banta, Gareld Howard; Johnson, Scott Daniel; Wang, Albert R., Programmable logic configuration for instruction extensions.
    상세보기
  114. Rupp Charle R., Reconfigurable computer architecture for use in signal processing applications.
    상세보기
  115. Vorbach, Martin, Reconfigurable elements.
    상세보기
  116. Vorbach, Martin, Reconfigurable elements.
    상세보기
  117. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
    상세보기
  118. Vorbach,Martin; M？nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.
    상세보기
  119. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  120. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  121. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  122. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  123. Vorbach,Martin, Reconfigurable sequencer structure.
    상세보기
  124. Trimberger Stephen M., Reprogrammable instruction set accelerator.
    상세보기
  125. Trimberger Stephen M., Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page tab.
    상세보기
  126. Vorbach, Martin; Bretz, Daniel, Router.
    상세보기
  127. Vorbach,Martin; Bretz,Daniel, Router.
    상세보기
  128. Vorbach Martin,DEX ; Munch Robert,DEX, Run-time reconfiguration method for programmable units.
    상세보기
  129. Vorbach,Martin; M？nch,Robert, Run-time reconfiguration method for programmable units.
    상세보기
  130. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
    상세보기
  131. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
    상세보기
  132. Chan Virginia M. ; Muller Stephen C. ; Berger Douglas M. ; Nguyen Chuong D., Selective configuration of operating programs stored in an application specific integrated circuit.
    상세보기
  133. Metzgen,Paul, Software-to-hardware compiler.
    상세보기
  134. Metzgen,Paul, Software-to-hardware compiler.
    상세보기
  135. Metzgen, Paul, Software-to-hardware compiler with symbol set inference analysis.
    상세보기
  136. Metzgen, Paul, Software-to-hardware compiler with symbol set inference analysis.
    상세보기
  137. Metzgen,Paul, Software-to-hardware compiler with symbol set inference analysis.
    상세보기
  138. Kanai, Yoshihiko, Supervisory control apparatus.
    상세보기
  139. Baxter Michael A., System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware.
    상세보기
  140. Baxter Michael A., System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization.
    상세보기
  141. Johnson, Tony L.; Shelton, Greg L., System and method for multi-level security on a network.
    상세보기
  142. Songer,Christopher; Eslick,Ian S.; French,Robert S., System and method for preparing software for execution in a dynamically configurable hardware environment.
    상세보기
  143. Panwar Ramesh ; Chamdani Joseph I., System for allocation of execution resources amongst multiple executing processes.
    상세보기
  144. Bonola Thomas J., System for implementing intelligent I/O processing in a multi-processor system by redirecting I/O messages to a target central processor selected from the multi-processor system.
    상세보기
  145. Gonzalez, Ricardo E.; Wang, Albert R., Systems and methods for selecting input/output configuration in an integrated circuit.
    상세보기
  146. Gonzalez, Ricardo E.; Wang, Albert R.; Banta, Gareld Howard, Systems and methods for software extensible multi-processing.
    상세보기
  147. McGettigan,Edward S.; Fross,Bradley K.; Peattie,Michael E., Systems and methods of utilizing virtual input and output modules in a programmable logic device.
    상세보기
  148. Stakutis, Christopher J.; Haselton, William, Term-based methods and apparatus for access to files on shared storage devices.
    상세보기
  149. Rupp,Charle' R., Transitive processing unit for performing complex operations.
    상세보기
  150. Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.
    상세보기
  151. Ahmad, Sagheer; Taylor, Bradley L.; Ansari, Ahmad R.; Knopp, Tomai, User-configurable error handling.
    상세보기
  152. Arnold,Jeffrey Mark; Banta,Gareld Howard; Johnson,Scott Daniel; Wang,Albert R., Video processing system with reconfigurable instructions.
    상세보기

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