이 특허를 인용한 특허 (22)

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2. Craske, Simon John; Grisenthwaite, Richard Roy; Stephens, Nigel John, Conditional selection of data elements.

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3. Craske, Simon John; Grisenthwaite, Richard Roy; Stephens, Nigel John, Conditional selection of data elements.

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4. Libby, Jeffrey G.; Frailong, Jean-Marc; Yeluri, Sharada; Huang, Jianhui; Keen, John; Nair, Rajesh, Emulation of multiple instruction sets.

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5. Tanikawa, Tadao, Generation and concurrent execution of a virtual task in an execution order determining system.

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6. Benayoun, Alain; Le Pennec, Jean-Francois; Pin, Claude; Michel, Patrick, Hardware device for executing programmable instructions based upon micro-instructions.

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7. Kakiage Touru,JPX ; Suzuki Masato,JPX, Information processing apparatus and method, and scheduling device for reducing inactivity due to wait state.

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8. Patel Sanjay ; Talcott Adam R. ; Cherabuddi Rajasekhar, Method and apparatus for branch target prediction.

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9. Jeppesen, Niels Gram; Uhler, G. Michael, Method and apparatus for clearing hazards using jump instructions.

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10. Jeppesen,Niels Gram; Uhler,G. Michael, Method and apparatus for clearing hazards using jump instructions.

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11. Bose Pradip ; Chan Kin Shing ; Le Hung Qui ; Wasmuth Robert Eric, Method and system for reducing average branch resolution time and effective misprediction penalty in a processor.

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12. Osborne, II, Theodore M.; Glik, Michael V.; Vahey, Walter G.; Baker, Caren H.; Friedman, George, Method and system for software object testing.

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13. Osborne, II, Theodore M.; Glik, Michael V.; Vahey, Walter G.; Baker, Caren H.; Friedman, George, Method and system for software object testing.

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14. Baker, Caren H.; Friedman, George; Glik, Michael V.; Vahey, Walter G., Method of providing software testing services.

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15. Thomas L. Drabenstott ; Gerald G. Pechanek ; Edwin F. Barry ; Charles W. Kurak, Jr., Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution.

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16. Rupley, II, Jeffrey P.; Brekelbaum, Edward A.; Grochowski, Edward T.; Black, Bryan P., Micro-operation generator for deriving a plurality of single-destination micro-operations from a given predicated instruction.

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17. Lee, Hoi-Jin, Partial match partial output cache for computer arithmetic operations.

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18. Shiraishi Mikio,JPX ; Saitou Masaki,JPX ; Okuda Yuji,JPX, Processor.

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19. Bluhm Mark W., Register file for registers with multiple addressable sizes using read-modify-write for register file update.

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20. Tran Thang M., Register file having multiple register storages for storing data from multiple data streams.

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21. Gerard M. Col ; G. Glenn Henry, Result forwarding cache.

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22. Gerard M. Col ; G. Glenn Henry, Result forwarding cache.

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