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Programmable digital signal processor for performing a plurality of signal processings 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/20
출원번호 US-0272749 (1994-07-11)
우선권정보 JP-0179594 (1993-07-21)
발명자 / 주소
  • Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX)
출원인 / 주소
  • Hitachi, Ltd. (Tokyo JPX 03)
인용정보 피인용 횟수 : 247  인용 특허 : 0

초록 ▼

A digital signal processor for processing various types of signals, such as an image signal and an audio signal, a basic signal processing part, a programmable logic part, and a bus for connecting these parts together. Circuit configuration data is transferred to the programmable logic part from an

대표청구항 ▼

A digital signal processor chip for performing a plurality of signal processings of audio and video input signal data in a data processing system having memory means and providing processed output data, comprising: said chip being connected to said system; a first processor part and a second progamm

이 특허를 인용한 특허 (247)

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  155. Muthujumaraswathy Kumaraguru ; Rostoker Michael D., Multimedia interface having a multimedia processor and a field programmable gate array.
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  156. Muthujumaraswathy, Kumaraguru; Rostoker, Michael D., Multimedia interface having a processor and reconfigurable logic.
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  157. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.
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  158. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.
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  159. Sasaki,Paul T.; Menon,Suresh M.; Ghia,Atul V.; Cory,Warren E.; Verma,Hare K.; Freidin,Philip M., Network physical layer with embedded multi-standard CRC generator.
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  160. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
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  161. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
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  162. Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.
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  163. Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.
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  164. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
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  165. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
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  166. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Christopher; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
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  167. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
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  168. Mejdrich, Eric O.; Schardt, Paul E.; Shearer, Robert A.; Tubbs, Matthew R., Parallelized streaming accelerated data structure generation.
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  169. Hickey, Mark J.; Muff, Adam J.; Tubbs, Matthew R.; Wait, Charles D., Performing vector multiplication.
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  170. Liu,Ming Kang, Physical medium dependent sub-system with shared resources for multiport xDSL system.
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  171. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  172. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  173. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.
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  174. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.
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  175. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.
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  176. Vorbach Martin,DEX ; Munch Robert,DEX, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like).
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  177. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
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  178. Martin Vorbach DE; Robert Munch DE, Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like).
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  179. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
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  180. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
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  181. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
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  182. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.
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  183. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.
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  184. Mauer, Volker; Langhammer, Martin, Programmable device with specialized multiplier blocks.
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  185. Fairman, Bruce A., Programmable first-in first-out (FIFO) memory buffer for concurrent data stream handling.
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  186. Schultz,David P.; Douglass,Stephen M.; Young,Steven P.; Herron,Nigel G.; Vashi,Mehul R.; Sowards,Jane W., Programmable gate array and embedded circuitry initialization and processing.
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  187. Douglass, Stephen M.; Young, Steven P.; Herron, Nigel G.; Vashi, Mehul R.; Sowards, Jane W., Programmable gate array having interconnecting logic to support embedded fixed logic circuitry.
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  188. Hickey, Mark J.; Mejdrich, Eric O.; Muff, Adam J.; Schardt, Paul E.; Shearer, Robert A.; Tubbs, Matthew R.; Wait, Charles D., Programmable integrated processor blocks.
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  189. Ansari, Ahmad R., Programmable interactive verification agent.
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  190. Dao,Khang Kim; Baxter,Glenn A., Programmable logic device including programmable interface core and central processing unit.
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  191. Dao,Khang Kim; Baxter,Glenn A., Programmable logic device including programmable interface core and central processing unit.
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  192. Dao,Khang Kim; Baxter,Glenn A., Programmable logic device including programmable interface core and central processing unit.
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  193. Liu, Ming-Kang, Programmable task scheduler.
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  194. Langhammer, Martin, QR decomposition in an integrated circuit device.
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  195. Mauer, Volker, QR decomposition in an integrated circuit device.
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  196. Pearson,Eric C., Reconfigurable computing based multi-standard video codec.
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  197. Vorbach, Martin, Reconfigurable elements.
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  198. Vorbach, Martin, Reconfigurable elements.
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  199. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
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  200. Vorbach,Martin; M？nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.
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  201. Vorbach, Martin, Reconfigurable sequencer structure.
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  202. Vorbach, Martin, Reconfigurable sequencer structure.
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  203. Vorbach, Martin, Reconfigurable sequencer structure.
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  204. Vorbach, Martin, Reconfigurable sequencer structure.
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  205. Vorbach,Martin, Reconfigurable sequencer structure.
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  206. Hudson Michael ; Moore Daniel L., Redefinable signal processing subsystem.
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  207. Trimberger Stephen M., Reprogrammable instruction set accelerator.
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  208. Trimberger Stephen M., Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page tab.
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  209. Vorbach, Martin; Bretz, Daniel, Router.
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  210. Vorbach,Martin; Bretz,Daniel, Router.
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  211. Vorbach Martin,DEX ; Munch Robert,DEX, Run-time reconfiguration method for programmable units.
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  212. Vorbach,Martin; M？nch,Robert, Run-time reconfiguration method for programmable units.
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  213. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
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  214. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
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  215. Liu,Ming Kang, Scaleable architecture for multiple-port, system-on-chip ADSL communications systems.
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  216. Yamaguchi, Yuji; Imai, Masatoshi; Noda, Toshiharu; Asari, Naosuke; Mitsunaga, Tomoo; Ohki, Mitsuharu; Ito, Kazumasa; Nagano, Hidetoshi; Arakawa, Sumito; Ito, Kei, Signal processing apparatus with signal control units and processor units operating based on different threads.
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  217. Yamashita, Kosei, Signal processing apparatus with user-configurable circuit configuration.
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  218. Langhammer, Martin; Dhanoa, Kulwinder, Solving linear matrices in an integrated circuit device.
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  219. Langhammer, Martin, Specialized processing block for implementing floating-point multiplier with subnormal operation support.
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  220. Xu, Lei; Mauer, Volker; Perry, Steven, Specialized processing block for programmable integrated circuit device.
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  221. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Lin, Yi-Wen, Specialized processing block for programmable logic device.
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  222. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Pelt, Robert L., Specialized processing block for programmable logic device.
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  223. Langhammer, Martin; Lee, Kwan Yee Martin; Nguyen, Triet M.; Streicher, Keone; Azgomi, Orang, Specialized processing block for programmable logic device.
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  224. Lee, Kwan Yee Martin; Langhammer, Martin; Lin, Yi-Wen; Nguyen, Triet M., Specialized processing block for programmable logic device.
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  225. Lee, Kwan Yee Martin; Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Specialized processing block for programmable logic device.
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  226. Langhammer, Martin, Specialized processing block with fixed- and floating-point structures.
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  227. Lai, Andrew W., Structures and methods for testing programmable logic devices having mixed-fabric architectures.
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  228. Lai,Andrew W., Structures and methods for testing programmable logic devices having mixed-fabric architectures.
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  229. Liu,Ming Kang, System and method for a family of digital subscriber line (XDSL) signal processing circuit operating with an internal clock rate that is higher than all communications ports operating with a pluralit.
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  230. Kiuchi Atsushi,JPX ; Hatano Yuji,JPX ; Baji Toru,JPX ; Noguchi Koki,JPX ; Akao Yasushi,JPX ; Baba Shiro,JPX, System for maintaining fixed-point data alignment within a combination CPU and DSP system.
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  231. Roussel, Patrice, System to perform horizontal additions.
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  232. Herron,Nigel G.; Thorne,Eric J.; Wang,Qingqi; Correale, Jr.,Anthony; Dick,Thomas Anderson, Testing a programmable logic device with embedded fixed logic using a scan chain.
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  233. Yin, Robert, Testing address lines of a memory controller.
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  234. Yin,Robert, Testing address lines of a memory controller.
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  235. Burnley, Richard P., Timing performance analysis.
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  236. Burnley,Richard P., Timing performance analysis.
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  237. Liu,Ming Kang, Transport convergence sub-system with shared resources for multiport xDSL system.
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  238. Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.
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  239. Douglass, Stephen M.; Sastry, Prasad L.; Vashi, Mehul R.; Yin, Robert, User configurable memory system having local and global memory blocks.
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  240. Ansari, Ahmad R.; Douglass, Stephen M.; Vashi, Mehul R.; Young, Steven P., User configurable on-chip memory system.
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  241. Cory, Warren E., Variable data width converter.
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  242. Cory, Warren E.; Verma, Hare K.; Ghia, Atul V.; Sasaki, Paul T.; Menon, Suresh M., Variable data width operation in multi-gigabit transceivers on a programmable logic device.
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  243. Cory, Warren E.; Verma, Hare K.; Ghia, Atul V.; Sasaki, Paul T.; Menon, Suresh M., Variable data width operation in multi-gigabit transceivers on a programmable logic device.
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  244. Spektor, Evgeny; Elias, Gili, Video data processing circuits and systems comprising programmable blocks or components.
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  245. Liu,Ming Kang, xDSL communications systems using shared/multi-function task blocks.
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  246. Liu,Ming Kang, xDSL function ASIC processor and method of operation.
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  247. Liu, Ming-Kang, xDSL symbol processor and method of operating same.
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