[특허]Method and apparatus for mapping memory as to operable and faulty locations

Method and apparatus for mapping memory as to operable and faulty locations 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-011/00
출원번호	US-0209580 (1994-03-11)
우선권정보	IT-0000155 (1993-03-12)
발명자 / 주소	Di Zenzo Maurizio (Rieti ITX) Pistilli Pasquale (Avezzano ITX) Salsano Adelio (Rome ITX)
출원인 / 주소	Texas Instruments Incorporated (Dallas TX 02)
인용정보	피인용 횟수 : 55 인용 특허 : 0

초록 ▼

System for enabling the use of semiconductor dynamic memories having faulty locations therein where the memory is organized in banks for forming an elementary information word. The system identifies all homologous address locations which are not faulty, and the non-faulty locations are then stored as a map in a non-volatile read-only-memory related to the memory bank so as to form a transcoding table. Access to the memory blocks involves the use of a central processing unit requesting access to a block identified by a sequential address. The system then provides for associating the material address of a block of the memory array to the logical address, this association or transcoding operation being carried out by the non-volatile read-only-memory.

대표청구항 ▼

A method for mapping operable homologous address locations in a semiconductor memory device having faulty locations so as to enable such semiconductor memory devices to be used, said method comprising: organizing the semiconductor memory device as at least one memory block having a plurality of memory banks to form an elementary information word; identifying all operable homologous address locations of the memory banks of the semiconductor memory device; utilizing areas of the memory block having a limited number of faulty locations by applying an error correction procedure implementing a modified Reed-Solomon algorithm having a generator polynomial g(x)=x4+a201.x3+a246.x2+a201.x+1 by translating a data string in such a manner as to move an error always to the first location of the data string; detecting and correcting errors by logic test circuits; establishing a map of the operable homologous address locations of the memory banks; storing the map of operable homologous address locations of the memory banks in a non-volatile memory as data content respectively associated with the memory bank, thereby forming a transcoding table of material addresses in the non-volatile memory; requesting access to a memory block identified by a sequential logical address; associating the sequential logical address of the memory block to a material address of the non-volatile memory; retrieving the data content of a selected material address from the non-volatile memory; and directly accessing the corresponding memory block enabled by the data content retrieved from the non-volatile memory at the selected material address.

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Method and apparatus for mapping memory as to operable and faulty locations 원문보기

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Method and apparatus for mapping memory as to operable and faulty locations 원문보기

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