[특허]Method of manufacturing resin-sealed semiconductor device, lead frame used in this method for mounting plurality of semi

Method of manufacturing resin-sealed semiconductor device, lead frame used in this method for mounting plurality of semi 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/495 H01L-023/34
출원번호	US-0213586 (1994-03-16)
우선권정보	JP-0141790 (1993-06-14)
발명자 / 주소	Hosokawa Ryuji (Yokohama JPX) Yanagida Satoru (Kawasaki JPX)
출원인 / 주소	Kabushiki Kaisha Toshiba (Kawasaki JPX 03)
인용정보	피인용 횟수 : 28 인용 특허 : 0

초록 ▼

According to a method of manufacturing a semiconductor device of this invention, a first lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads. A second lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads as in the first lead frame portion coupled to the second lead frame portion through a coupling portion. The first and second lead frame portions are folded at the coupling portion and superposed each other such that the two semiconductor elements oppose each other. At this time, the plurality of inner and outer leads of the first and second lead frames are alternately and adjacently arranged. Each electrode of the semiconductor elements is connected to a corresponding inner lead. The superposed first and second lead frames are sealed with a mold resin while leaving end portions of the plurality of outer leads of the first and second lead frames.

대표청구항 ▼

A lead frame comprising: a lead frame member comprising a first lead frame portion and a second lead frame portion; said first lead frames portion being arranged along a longitudinal direction of said lead frame member and having a first recess serving as a first bed portion for mounting a semiconductor element, and a first lead group comprising a plurality of inner leads extending in at least one direction around said bed portion and arranged in parallel at substantially equal intervals and a plurality of outer leads respectively connected to said inner leads; and said second lead frame portion having a second recess serving as a second bed portion for mounting a semiconductor element, and a second lead group comprising a plurality of inner leads and a plurality of outer leads respectively connected to said inner leads, said second lead frame portion being connected to said first lead frame portion through a coupling portion of said lead frame member, and the plurality of inner leads and the plurality of outer leads of said second lead group being alternately arranged between the plurality of inner leads and the plurality of outer leads extending in a same direction in said first lead group when said second bed portion is superposed on said first bed portion of said first lead frame portion so as to oppose each other.

이 특허를 인용한 특허 (28)

Leonard E. Mess, Ball grid array (BGA) encapsulation mold.
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Mess Leonard E., Ball grid array (BGA) encapsulation mold.
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Mess Leonard E., Ball grid array (BGA) encapsulation mold.
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Mess Leonard E., Ball grid array (BGA) encapsulation mold.
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Mess, Leonard E., Encapsulation method in a molding machine for an electronic device.
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Kuah, Hsian Pang; Phua, Jenny, Inverted lead frame in substrate.
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Ahmad Syed Sajid, Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes.
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Ahmad Syed Sajid, Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and methods of designing and fabricating such leadframes.
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Ahmad, Syed Sajid, Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and methods of designing and fabricating such leadframes.
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Syed Sajid Ahmad, Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and methods of designing and fabricating such leadframes.
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Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts.
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Moden, Walter, Method for fabricating semiconductor packages with stacked dice and leadframes.
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Leonard E. Mess, Methods for ball grid array (BGA) encapsulation mold.
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Landau, Stefan; Mahler, Joachim; Wowra, Thomas, Multi-chip module.
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Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Multi-dice chip scale semiconductor components.
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Farnworth, Warren M.; Wood, Alan G.; Hiatt, William M.; Wark, James M.; Hembree, David R.; Kirby, Kyle K.; Benson, Pete A., Multi-dice chip scale semiconductor components and wafer level methods of fabrication.
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Klein,Dean A.; Wood,Alan G.; Doan,Trung Tri, Semiconductor component having multiple stacked dice.
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Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Semiconductor component having plate and stacked dice.
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Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Semiconductor component having plate, stacked dice and conductive vias.
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Klein,Dean A.; Wood,Alan G.; Doan,Trung Tri, Semiconductor components having stacked dice.
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Moden, Walter, Semiconductor package having stacked dice and leadframes and method of fabrication.
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Masachika Masuda JP; Tamaki Wada JP; Michiaki Sugiyama JP; Hirotaka Nishizawa JP; Toshio Sugano JP; Yasushi Takahashi JP; Masayasu Kawamura JP, Stacked semiconductor device including improved lead frame arrangement.
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Masuda Masachika,JPX ; Wada Tamaki,JPX ; Sugiyama Michiaki,JPX ; Nishizawa Hirotaka,JPX ; Sugano Toshio,JPX ; Takahashi Yasushi,JPX ; Kawamura Masayasu,JPX, Stacked semiconductor device including improved lead frame arrangement.
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Masuda, Masachika; Wada, Tamaki; Sugiyama, Michiaki; Nishizawa, Hirotaka; Sugano, Toshio; Takahashi, Yasushi; Kawamura, Masayasu, Stacked semiconductor device including improved lead frame arrangement.
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Masuda,Masachika; Wada,Tamaki; Sugiyama,Michiaki; Nishizawa,Hirotaka; Sugano,Toshio; Takahashi,Yasushi; Kawamura,Masayasu, Stacked semiconductor device including improved lead frame arrangement.
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Masuda,Masachika; Wada,Tamaki; Sugiyama,Michiaki; Nishizawa,Hirotaka; Sugano,Toshio; Takahashi,Yasushi; Kawamura,Masayasu, Stacked semiconductor device including improved lead frame arrangement.
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Klein,Dean A.; Wood,Alan G.; Doan,Trung Tri, System having semiconductor component with multiple stacked dice.
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Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Wafer level methods for fabricating multi-dice chip scale semiconductor components.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Method of manufacturing resin-sealed semiconductor device, lead frame used in this method for mounting plurality of semi 원문보기

초록 ▼

대표청구항 ▼

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Method of manufacturing resin-sealed semiconductor device, lead frame used in this method for mounting plurality of semi 원문보기

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연구과제 타임라인

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이 특허를 인용한 특허 (28)

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