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Method of making a transistor having easily controllable impurity profile 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/20
출원번호 US-0242147 (1994-05-13)
우선권정보 JP-0324799 (1990-11-27)
발명자 / 주소
  • Koh Risho (Tokyo JPX)
출원인 / 주소
  • NEC Corporation (JPX 03)
인용정보 피인용 횟수 : 150  인용 특허 : 0

초록

On the substrate of an integrated circuit chip is deposited a first insulating layer in which a low resistivity semiconductor region is subsequently formed. An insulating film is formed on a side wall of the low resistivity semiconductor region. A slit is formed in the first insulating layer so that

대표청구항

A method of fabricating a transistor, comprising the steps of: providing a substrate of a first conductivity type; forming a first insulating layer on the substrate; forming a conductive region on the first insulating layer; forming a second insulating layer on the conductive region: successively re

이 특허를 인용한 특허 (150)

  1. Radosavljevic,Marko; Majumdar,Amlan; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark L.; Brask,Justin K.; Shah,Uday; Datta,Suman; Chau,Robert S., Block contact architectures for nanoscale channel transistors.
  2. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  3. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  4. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  5. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  6. Forbes, Leonard, DRAM with nanofin transistors.
  7. Forbes, Leonard, DRAM with nanofin transistors.
  8. Bai, Jie; Lochtefeld, Anthony J.; Park, Ji-Soo, Defect reduction using aspect ratio trapping.
  9. Bai, Jie; Lochtefeld, Anthony J.; Park, Ji-Soo, Defect reduction using aspect ratio trapping.
  10. Bai, Jie; Park, Ji-Soo; Lochtefeld, Anthony J., Defect reduction using aspect ratio trapping.
  11. Lochtefeld, Anthony J., Devices formed from a non-polar plane of a crystalline material and method of making the same.
  12. Lochtefeld, Anthony J., Devices formed from a non-polar plane of a crystalline material and method of making the same.
  13. Lochtefeld, Anthony J., Devices formed from a non-polar plane of a crystalline material and method of making the same.
  14. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  15. Lochtefeld, Anthony J., Diode-based devices and methods for making the same.
  16. Lochtefeld, Anthony J., Diode-based devices and methods for making the same.
  17. Lochtefeld, Anthony J., Diode-based devices and methods for making the same.
  18. Lochtefeld, Anthony J., Diode-based devices and methods for making the same.
  19. Lochtefeld, Anthony J., Diode-based devices and methods for making the same.
  20. Park, Ji-Soo, Epitaxial growth of crystalline material.
  21. Park, Ji-Soo, Epitaxial growth of crystalline material.
  22. Park, Ji-Soo; Fiorenza, James G., Fabrication and structures of crystalline material.
  23. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  24. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  25. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  26. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  27. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  28. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  29. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  30. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  31. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  32. Buynoski,Matthew S.; An,Judy Xilin; Yu,Bin, FinFET device with multiple channels.
  33. Buynoski, Matthew S.; An, Judy Xilin; Wang, Haihong; Yu, Bin, FinFET device with multiple fin structures.
  34. Cheng, Zhiyuan; Fiorenza, James; Hydrick, Jennifer M.; Lochtefeld, Anthony J.; Park, Ji-Soo; Bai, Jie; Li, Jizhong, Formation of devices by epitaxial layer overgrowth.
  35. Hydrick, Jennifer M.; Li, Jizhong; Cheng, Zhinyuan; Fiorenza, James; Bai, Jie; Park, Ji-Soo; Lochtefeld, Anthony J., Formation of devices by epitaxial layer overgrowth.
  36. Forbes, Leonard, Grown nanofin transistors.
  37. Shaheen,Mohamad A.; Doyle,Brian; Dutta,Suman; Chau,Robert S.; Tolchinsky,Peter, High mobility tri-gate devices and methods of fabrication.
  38. Ye, Peide; Cheng, Zhiyuan; Xuan, Yi; Wu, Yanqing; Adekore, Bunmi; Fiorenza, James, InP-based transistor fabrication.
  39. Ye, Peide; Cheng, Zhiyuan; Xuan, Yi; Wu, Yanqing; Adekore, Bunmi; Fiorenza, James, InP-based transistor fabrication.
  40. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  41. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  42. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  43. Datta,Suman; Brask,Justin K.; Kavalieros,Jack; Doyle,Brian S.; Dewey,Gilbert; Doczy,Mark L.; Chau,Robert S., Lateral undercut of metal gate in SOI device.
  44. Lochtefeld, Anthony J., Lattice-mismatched semiconductor structures and related methods for device fabrication.
  45. Lochtefeld, Anthony J., Lattice-mismatched semiconductor structures and related methods for device fabrication.
  46. Li, Jizhong; Lochtefeld, Anthony J., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  47. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  48. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  49. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  50. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  51. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  52. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  53. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  54. Li, Jizhong; Lochtefeld, Anthony J., Light-emitter-based devices with lattice-mismatched semiconductor structures.
  55. Forbes, Leonard, Logic array and dynamic logic method.
  56. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  57. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  58. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  59. Lin, Ming-Ren; Wang, Haihong; Yu, Bin, Method for forming structures in finfet devices.
  60. Cheng, Zhiyuan; Fiorenza, James; Sheen, Calvin; Lochtefeld, Anthony J., Method for semiconductor sensor structures with reduced dislocation defect densities.
  61. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  62. Adkisson,James W.; Agnello,Paul D.; Ballantine,Arne W.; Divakaruni,Rama; Jones,Erin C.; Nowak,Edward J.; Rankin,Jed H., Method of fabricating semiconductor side wall fin.
  63. Adkisson,James W.; Agnello,Paul D.; Ballantine,Arne W.; Divakaruni,Rama; Jones,Erin C.; Nowak,Edward J.; Rankin,Jed H., Method of fabricating semiconductor side wall fin.
  64. Adkisson,James W.; Agnello,Paul D.; Ballantine,Arne W.; Divakaruni,Rama; Jones,Erin C.; Nowak,Edward J.; Rankin,Jed H., Method of fabricating semiconductor side wall fin.
  65. Brask,Justin K.; Doyle,Brian S.; Kavalleros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Method of forming a metal oxide dielectric.
  66. Brask, Justin K.; Doyle, Brian S.; Kavalieros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material.
  67. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
  68. Darwish Mohamed N. (Saratoga CA) Williams Richard K. (Cupertino CA), Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentrati.
  69. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  70. Thomas Schulz DE; Thomas Augle DE; Wolfgang Rosner DE; Lothar Risch DE, Method of producing a vertical MOS transistor.
  71. Pradeep, Yelehanka; Zheng, Jia Zhen; Chan, Lap; Quek, Elgin; Sundaresan, Ravi; Pan, Yang; Meng, James Lee Yong; Keung, Ying, Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel.
  72. James Yong Meng Lee SG; Ying Keung Leung HK; Yelehanka Ramachandramurthy Pradeep SG; Jia Zhen Zheng SG; Lap Chan ; Elgin Quek SG; Ravi Sundaresan ; Yang Pan SG, Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers.
  73. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  74. Cheng, Zhiyuan; Fiorenza, James; Sheen, Calvin; Lochtefeld, Anthony J., Methods for semiconductor sensor structures with reduced dislocation defect densities.
  75. Lochtefeld, Anthony J., Methods of forming semiconductor diodes by aspect ratio trapping with coalesced films.
  76. Forbes, Leonard, Monotonic dynamic-static pseudo-NMOS logic circuit.
  77. Zhang,Yuegang; Doyle,Brian S.; Bourianoff,George I., Multi-gate carbon nano-tube transistors.
  78. Fiorenza, James; Lochtefeld, Anthony J., Multi-junction solar cells.
  79. Fiorenza, James; Lochtefeld, Anthony J., Multi-junction solar cells.
  80. Layman,Paul Arthur; McMacken,John Russell; Thomson,J. Ross; Chaudhry,Samir; Zhao,Jack Qingsheng, Multiple operating voltage vertical replacement-gate (VRG) transistor.
  81. Forbes, Leonard, Nanofin transistors with crystalline semiconductor fins.
  82. Li, Jizhong, Nitride-based multi-junction solar cell modules and methods for making the same.
  83. Li, Jizhong, Nitride-based multi-junction solar cell modules and methods for making the same.
  84. Doyle, Brian S.; Datta, Suman; Jin, Been Yih; Chau, Robert, Non-planar MOS structure with a strained channel region.
  85. Doyle,Brian S.; Datta,Suman; Jin,Been Yih; Chau,Robert, Non-planar MOS structure with a strained channel region.
  86. Doyle,Brian S; Datta,Suman; Jin,Been Yih; Zelick,Nancy M; Chau,Robert, Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow.
  87. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Datta,Suman; Jin,Been Yih, Nonplanar device with stress incorporation layer and method of fabrication.
  88. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  89. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  90. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  91. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  92. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  93. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  94. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  95. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  96. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  97. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  98. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  99. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  100. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  101. Brask,Justin K.; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  102. Li, Jizhong; Lochtefeld, Anthony J.; Sheen, Calvin; Cheng, Zhiyuan, Photovoltaics on silicon.
  103. Hydrick, Jennifer M.; Fiorenza, James, Polishing of small composite semiconductor materials.
  104. Hydrick, Jennifer M.; Fiorenza, James, Polishing of small composite semiconductor materials.
  105. Hydrick, Jennifer M.; Fiorenza, James G., Polishing of small composite semiconductor materials.
  106. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  107. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  108. Fraboulet,David; Deleonibus,Simon, Processes for making a single election transistor with a vertical channel.
  109. Cheng, Zhiyuan; Sheen, Calvin, Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures.
  110. Cheng, Zhiyuan; Sheen, Calvin, Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures.
  111. Cheng, Zhiyuan; Sheen, Calvin, Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures.
  112. Cheng, Zhiyuan; Sheen, Calvin, Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures.
  113. Cheng, Zhiyuan; Sheen, Calvin, Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures.
  114. Cheng, Zhiyuan, Reduction of edge effects from aspect ratio trapping.
  115. Cheng, Zhiyuan, Reduction of edge effects from aspect ratio trapping.
  116. Cheng, Zhiyuan, Reduction of edge effects from aspect ratio trapping.
  117. Cheng, Zhiyuan, Reduction of edge effects from aspect ratio trapping.
  118. Cheng, Zhiyuan, Reduction of edge effects from aspect ratio trapping.
  119. Anderson, Brent A.; Nowak, Edward J.; Rainey, BethAnn, Semiconductor device having freestanding semiconductor layer.
  120. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  121. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  122. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  123. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  124. Zhao, Sam Ziqun; Hui, Frank, Semiconductor device with a variable-width vertical channel formed through a plurality of semiconductor layers.
  125. Zhao, Sam Ziqun; Hui, Frank, Semiconductor device with a vertical channel formed through a plurality of semiconductor layers.
  126. Lochtefeld, Anthony J., Semiconductor diodes fabricated by aspect ratio trapping with coalesced films.
  127. Lochtefeld, Anthony J., Semiconductor diodes fabricated by aspect ratio trapping with coalesced films.
  128. Lochtefeld, Anthony J., Semiconductor diodes fabricated by aspect ratio trapping with coalesced films.
  129. Cheng, Zhiyuan; Fiorenza, James G.; Sheen, Calvin; Lochtefeld, Anthony, Semiconductor sensor structures with reduced dislocation defect densities.
  130. Cheng, Zhiyuan; Fiorenza, James; Sheen, Calvin; Lochtefeld, Anthony J., Semiconductor sensor structures with reduced dislocation defect densities.
  131. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  132. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  133. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  134. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  135. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  136. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  137. Wang,Haihong; Ahmed,Shibly S.; Lin,Ming Ren; Yu,Bin, Systems and methods for forming multiple fin structures using metal-induced-crystallization.
  138. Darwish Mohamed N. ; Williams Richard K., Trench MOSFET with multi-resistivity drain to provide low on-resistance.
  139. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman, Tri-gate devices and methods of fabrication.
  140. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman; Hareland, Scott A., Tri-gate devices and methods of fabrication.
  141. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  142. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  143. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman; Hareland,Scott A., Tri-gate devices and methods of fabrication.
  144. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman; Hareland,Scott A., Tri-gate devices and methods of fabrication.
  145. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  146. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  147. Chau,Robert; Datta,Suman; Doyle,Brian S; Jin,Been Yih, Tri-gate transistors and methods to fabricate same.
  148. Shaheen, Mohamad A.; Rachmady, Willy; Tolchinsky, Peter, Ultra-thin oxide bonding for S1 to S1 dual orientation bonding.
  149. Yang Ching-Nan,TWX ; Liu Chia-Chen,TWX, Vertical thin film transistor.
  150. Chung, Woo Young, Vertical transistor of semiconductor device and method for forming the same.
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