이 특허를 인용한 특허 (50)

1. Chen, Hsin-Liang; Tu, Shuo-Lun, Bi-directional bipolar junction transistor for high voltage electrostatic discharge protection.

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2. Chen, Hsin-Liang; Tu, Shuo-Lun, Bi-directional bipolar junction transistor for high voltage electrostatic discharge protection.

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3. Hébert, François, Bottom anode Schottky diode structure and method.

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4. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.

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5. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.

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6. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Chip structure and process for forming the same.

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7. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.

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8. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.

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9. Otake, Seiji; Takeda, Yasuhiro; Miyamoto, Yuta, Circuit including a resistive element, a diode, and a switch and a method of using the same.

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10. Kamiya Hiroshi,JPX, Diode circuit for clamping the signals on a transmission line to a predetermined potential.

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11. Sawahata, Kouichi, ESD protection element.

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12. Cai, Jun; Hua, Guang Ping; Song, Jun; Lo, Keng Foo, ESD protection structure.

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13. Zhan, Rouying; Gill, Chai Ean; Hong, Changsoo; Kaneshiro, Michael H., ESD protection with asymmetrical bipolar-based device.

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14. Riess, Philipp; Feick, Henning; Wendel, Martin, Electronic component and a system and method for producing an electronic component.

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15. Su, Xian-Jun; Lin, Ching-Chung, Electrostatic discharge protection circuit and electronic device using the same.

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16. Crippen Richard E., Electrostatic discharge protection circuit and method.

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17. Luo, Min Yih; Terrill, Kyle; Werres, Chrisoph, Electrostatic discharge protection circuit for integrated circuits.

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18. Jung Hyuck-Chai,KRX, Electrostatic discharge protective circuit for semiconductor device.

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19. Ng Kwok Kwok, Electrostatic protection devices for protecting semiconductor integrated circuitry.

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20. Demirlioglu, Esin Kutlu; Luo, Min-Yih, Floating gate structure with high electrostatic discharge performance.

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21. Zdebel,Peter J.; Dow,Diann Michelle, High energy ESD structure and method.

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22. Vashchenko, Vladislav; Concannon, Ann; Hopper, Peter J.; ter Beek, Marcel, High holding voltage ESD protection structure for BiCMOS technology.

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23. Holberg Douglas R. ; Itani Nadi R. ; Welland David R., High voltage input pad system.

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24. Holberg Douglas R. ; Itani Nadi R. ; Welland David R., High voltage input pad system.

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25. Roberto Sung ; Jau-Wen Chen, Input and power protection circuit implemented in a complementary metal oxide semiconductor process using salicides.

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26. Okamoto Toshiharu,JPX, Input protection circuit having load resistor implemented by p-channel MIS transistor.

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27. Cottin, Denis; Schwartzmann, Thierry; Vildeuil, Jean-Charles; Martinet, Bertrand; Taupin, Sophie; Marin, Mathieu, Integrated circuit comprising a substrate and a resistor.

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28. Hsu Sheng Teng ; Fujii Katsumasa,JPX ; Kawazoe Hidechika,JPX ; Lee Jong Jan, Locos MOS device for ESD protection.

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29. Lin Geeng-Lih,TWX ; Der Ming-Dou,TWX, Method of forming an ESD protection device.

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30. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.

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31. Chang Kun-Zen,TWX ; Lin Ching-Yuan,TWX, Protection device structure for low supply voltage applications.

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32. Tsukanov, Vladimir; Zommer, Nathan, Rugged and fast power MOSFET and IGBT.

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33. Tsukanov, Vladimir; Zommer, Nathan, Rugged and fast power MOSFET and IGBT.

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34. Liu Meng-Hwang,TWX ; Lai Chen-Shang,TWX ; Lu Tao-Cheng,TWX ; Wang Mam-Tsung,TWX, Self protected stacked NMOS with non-silicided region to protect mixed-voltage I/O pad from ESD damage.

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35. Kikuchi, Shuichi; Okawa, Shigeaki; Nakaya, Kiyofumi; Tanaka, Shuji, Semiconductor device.

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36. Mita, Keiji; Tamada, Yasuhiro; Takahashi, Masao; Maruyama, Takao, Semiconductor device.

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37. Sawahata, Kouichi; Sato, Masaharu, Semiconductor device.

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38. Lee, Ming-Chang; Sun, Chung-Tsun; Chang, Chia-Der, Semiconductor device structure and method for forming the same.

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39. Lee, Ming-Chang; Sun, Chung-Tsun; Chang, Chia-Der, Semiconductor device structure and method for forming the same.

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40. Fujii Takeo,JPX ; Narita Kaoru,JPX ; Horiguchi Yoko,JPX, Semiconductor integrated circuit with protection circuit against electrostatic discharge.

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41. Ichikawa, Kenji, Semiconductor integrated device including an electrostatic breakdown protection circuit having uniform electrostatic surge response.

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42. Paul, Amit; Darwish, Mohamed N., Semiconductor on insulator devices containing permanent charge.

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43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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49. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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50. Chen, Qufei; Xu, Robert; Terrill, Kyle; Pattanayak, Deva, Trench polysilicon diode.

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