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Method for making an electronics module having air bridge protection without large area ablation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B23K-026/00
  • H01L-021/60
  • H05K-003/30
출원번호 US-0304920 (1994-09-13)
발명자 / 주소
  • Cole
  • Jr. Herbert S. (Burnt Hills NY) Sitnik-Nieters Theresa A. (Rexford NY)
출원인 / 주소
  • Martin Marietta Corporation (King of Prussia PA 02)
인용정보 피인용 횟수 : 49  인용 특허 : 0

초록 ▼

In a method for preserving an air bridge structure on an integrated circuit chip, without sacrificing metallization routing area in an overlying high density interconnect structure, a protective layer is sublimed over the air bridge to provide mechanical strength while preventing contamination and d

대표청구항 ▼

A method for making an electronics module, comprising the steps of: (1) disposing a plurality of electronic chips on a substrate surface, at least some of the chips including contact pads, and at least one of the chips including a sensitive structure; (2) encapsulating the sensitive structure with a

이 특허를 인용한 특허 (49)

  1. Edward Allyn Burton, Alignment of vias in circuit boards or similar structures.
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  2. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Chip package.
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  3. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
    상세보기
  4. Bedinger, John M.; Moore, Michael A., Environmental protection coating system and method.
    상세보기
  5. Bedinger, John M.; Moore, Michael A., Environmental protection coating system and method.
    상세보기
  6. Bedinger, John M.; Moore, Michael A., Environmental protection coating system and method.
    상세보기
  7. Saia Richard Joseph ; Durocher Kevin Matthew ; Cole Herbert Stanley, Flexible interconnect film including resistor and capacitor layers.
    상세보기
  8. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
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  9. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
    상세보기
  10. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
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  11. Field, Dean L.; Stone, Charles N.; Bruner, Michael W., Integrated circuit having one or more conductive devices formed over a SAW and/or MEMS device.
    상세보기
  12. Kornrumpf, William; Claydon, Glenn; Dasgupta, Samhita; Filkins, Robert; Forman, Glenn; Iannotti, Joseph; Nielsen, Matthew Christian, Integrated optoelectronic circuit and method of fabricating the same.
    상세보기
  13. Chen, Kun-Ching; Yeh, Yung I, Lead-bond type chip package and manufacturing method thereof.
    상세보기
  14. Chen,Kun Ching; Yeh,Yung I, Lead-bond type chip package and manufacturing method thereof.
    상세보기
  15. Kun-Ching Chen TW; Yung I Yeh TW, Lead-bond type chip package and manufacturing method thereof.
    상세보기
  16. Saia Richard Joseph ; Durocher Kevin Matthew ; Cole Herbert Stanley, Method for fabricating a flexible interconnect film with resistor and capacitor layers.
    상세보기
  17. Takayuki Suyama JP, Method for fabricating a multichip module to improve signal transmission.
    상세보기
  18. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
    상세보기
  19. Sasaki Hajime (Itami JPX), Method for fabricating microwave semiconductor integrated circuit.
    상세보기
  20. Kokubun, Katsunori; Azeyanagi, Kunihiko; Tsukahara, Toshiyuki, Method for forming fine through hole conduction portion of circuit board.
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  21. Aigner, Robert; Franosch, Martin; Meckes, Andreas; Oppermann, Klaus-G?nter; Strasser, Marc, Method for generating a protective cover for a device.
    상세보기
  22. Fran.cedilla.ois Gueissaz CH, Method for hermetically encapsulating microsystems in situ.
    상세보기
  23. Kornrumpf, William; Claydon, Glenn; Dasgupta, Samhita; Filkins, Robert; Forman, Glenn; Iannotti, Joseph; Nielsen, Matthew Christian, Method of fabricating an integrated optoelectronic circuit.
    상세보기
  24. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Method of fabricating chip package.
    상세보기
  25. Chua,Swee Kwang; Low,Siu Waf; Chia,Yong Poo; Eng,Meow Koon; Neo,Yong Loo; Boon,Suan Jeung; Huang,Suangwu; Zhou,Wei, Method of making multichip wafer level packages and computing systems incorporating same.
    상세보기
  26. Shim Il Kwon,KRX ; Ha Sun Ho,KRX, Method of manufacturing ball grid array semiconductor package.
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  27. Kato Makiko,JPX ; Iwasaki Yasukazu,JPX ; Uchiyama Makoto,JPX, Method of producing device having minute structure.
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  28. Quek Shyue Fong,MYX ; Ang Ting Cheong,SGX ; Chan Lap ; Loong Sang Yee,SGX, Method to form, and structure of, a dual damascene interconnect device.
    상세보기
  29. Bedinger, John M.; Moore, Michael A., Methods of making an environment protection coating system.
    상세보기
  30. Samples, Benjamin A., Multi-layer thick-film RF package.
    상세보기
  31. Takayuki Suyama JP, Multichip module.
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  32. Sasaki Makoto,JPX, Multilevel interconnection structure having an air gap between interconnects.
    상세보기
  33. Bedinger, John M.; Moore, Michael A.; Hallock, Robert B.; Alavi, Kamal Tabatabaie; Kazior, Thomas E., Passivation layer for a circuit device and method of manufacture.
    상세보기
  34. Bedinger, John; Moore, Michael A.; Hallock, Robert B; Tabatabaie, Kamal; Kazior, Thomas E., Passivation layer for a circuit device and method of manufacture.
    상세보기
  35. Delgado Jose Avelino ; Gaul Stephen Joseph, Pre-bond cavity air bridge.
    상세보기
  36. Samples, Benjamin A., RF package.
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  37. Takahashi, Yoshikazu; Suzuki, Masami; Kimura, Masaru, Semiconductor device having a chip-size package.
    상세보기
  38. Wojnarowski Robert John, Semiconductor interconnect structure for high temperature applications.
    상세보기
  39. Wojnarowski Robert John, Semiconductor interconnect structure for high temperature applications.
    상세보기
  40. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
    상세보기
  41. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
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  42. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
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  43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  49. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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