[특허]Method for forming capped copper electrical interconnects

Method for forming capped copper electrical interconnects 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	C25D-005/02 H01L-021/288
출원번호	US-0440413 (1995-05-12)
발명자 / 주소	Farooq Mukta S. (Hopewell Junction NY) Kaja Suryanarayana (Hopewell Junction NY) Perfecto Eric D. (Poughkeepsie NY) White George E. (Hoffman Estates IL)
출원인 / 주소	International Business Machines Corporation (Armonk NY 02)
인용정보	피인용 횟수 : 64 인용 특허 : 0

초록 ▼

The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

대표청구항 ▼

A method of making capped electrical interconnect comprising the steps of: (a) depositing at least one seed layer on a substrate, (b) depositing at least one resist layer over said at least one seed layer, (c) exposing and developing said at least one resist layer so as to define at least one opening in said at least one resist layer such that a portion of said at least one seed layer is exposed, (d) depositing copper in said at least one opening to define electrical interconnects, (e) thermally treating said substrate through at least one thermal cycle so that said resist separates from said deposited copper, and the side walls of said deposited copper are exposed, (f) capping said deposited copper electrical interconnect and the side walls thereof with at least one metallic capping material, (g) removing said at least one resist layer such that at least a portion of said at least one seed layer underneath said at least one resist layer is exposed, and (h) removing said exposed portion of said at least one seed layer, and thereby forming said capped electrical interconnect.

이 특허를 인용한 특허 (64)

Woodruff, Daniel J.; Hanson, Kyle M.; Eudy, Steve L.; Weber, Curtis A.; Harris, Randy, Adaptable electrochemical processing chamber.
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Cohen, Uri, Advanced seed layers for interconnects.
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Cohen,Uri, Advanced seed layery for metallic interconnects.
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Chen,Linlin; Wilson,Gregory J.; McHugh,Paul R.; Weaver,Robert A.; Ritzdorf,Thomas L., Apparatus and method for electrochemically depositing metal on a semiconductor workpiece.
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Chen LinLin, Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece.
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Chen, LinLin, Apparatus and method for electrolytically depositing a metal on a workpiece.
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Chen LinLin, Apparatus and method for electrolytically depositing copper on a semiconductor workpiece.
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Chen, Linlin, Apparatus and method for electrolytically depositing copper on a semiconductor workpiece.
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Peace, Steven L., Apparatus and method for regulating fluid flows, such as flows of electrochemical processing fluids.
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Hanson,Kyle M., Apparatus and methods for electrochemical processing of microelectronic workpieces.
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Hanson,Kyle M.; Ritzdorf,Thomas L.; Wilson,Gregory J.; McHugh,Paul R., Apparatus and methods for electrochemical processing of microelectronic workpieces.
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Hanson,Kyle M.; Ritzdorf,Thomas L.; Wilson,Gregory J.; McHugh,Paul R., Apparatus and methods for electrochemical processing of microelectronic workpieces.
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Cohen, Uri, Apparatus for depositing seed layers.
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Robert W. Batz, Jr. ; Scot Conrady ; Thomas L. Ritzdorf, Apparatus for high deposition rate solder electroplating on a microelectronic workpiece.
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Cohen, Uri, Apparatus for making interconnect seed layers and products.
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O'Brien,Kevin P.; Brask,Justin K., Capping of copper structures in hydrophobic ILD using aqueous electro-less bath.
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Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
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Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
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Hanson, Kyle M.; Klocke, John L., Chambers, systems, and methods for electrochemically processing microfeature workpieces.
상세보기
Klocke,John; Hanson,Kyle M, Chambers, systems, and methods for electrochemically processing microfeature workpieces.
상세보기
Klocke,John; Hanson,Kyle M, Chambers, systems, and methods for electrochemically processing microfeature workpieces.
상세보기
Daniel Charles Edelstein ; James McKell Edwin Harper ; Chao-Kun Hu ; Andrew H. Simon ; Cyprian Emeka Uzoh, Copper interconnection structure incorporating a metal seed layer.
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Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
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Woodruff,Daniel J.; Hanson,Kyle M., Electroplating apparatus with segmented anode array.
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Woodruff,Daniel J.; Hanson,Kyle M., Electroplating apparatus with segmented anode array.
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Kevin S. Petrarca ; Donald Canaperi ; Mahadevaiyer Krishnan ; Kenneth Jay Stein ; Richard P. Volant, Encapsulated metal structures for semiconductor devices and MIM capacitors including the same.
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Petrarca, Kevin S.; Canaperi, Donald; Krishnan, Mahadevaiyer; Stein, Kenneth Jay; Volant, Richard P., Encapsulated metal structures for semiconductor devices and MIM capacitors including the same.
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Yang, Chih-Chao; Horak, David V.; Koburger, Charles W.; Ponoth, Shom, Integrated circuit structure having selectively formed metal cap.
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Cohen, Uri, Metallic interconnects products.
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Farnworth, Warren M.; Duesman, Kevin G., Method and apparatus for electrolytic plating of surface metals.
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Chen, Linlin; Wilson, Gregory J.; McHugh, Paul R.; Weaver, Robert A.; Ritzdorf, Thomas L., Method for electrochemically depositing metal on a semiconductor workpiece.
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Chen Linlin, Method for electrolytically depositing copper on a semiconductor workpiece.
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Ritzdorf, Thomas L.; Graham, Lyndon W., Method for filling recessed micro-structures with metallization in the production of a microelectronic device.
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Ritzdorf,Thomas L.; Graham,Lyndon W., Method for filling recessed micro-structures with metallization in the production of a microelectronic device.
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Batz, Jr., Robert W.; Conrady, Scot; Ritzdorf, Thomas L., Method for high deposition rate solder electroplating on a microelectronic workpiece.
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Hongo, Akihisa; Nagai, Mizuki; Ohno, Kanji; Kimizuka, Ryoichi; Maruyama, Megumi, Method for plating a first layer on a substrate and a second layer on the first layer.
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Ritzdorf,Thomas L.; Eudy,Steve L.; Wilson,Gregory J.; McHugh,Paul R.; Weaver,Robert A.; Aegerter,Brian; Dundas,Curt; Peace,Steven L., Methods and apparatus for processing microelectronic workpieces using metrology.
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Collins,Dale W., Microelectronic workpiece for electrochemical deposition processing and methods of manufacturing and using such microelectronic workpieces.
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Cohen,Uri, Multiple seed layers for interconnects.
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Hu,Zhongmin; Ritzdorf,Thomas L.; Graham,Lyndon W., Platinum alloy using electrochemical deposition.
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Gaudiello,John G.; Herard,James D.; Konrad,John J.; McKeveny,Jeffrey; Wells,Timothy L., Process for manufacturing a printed wiring board.
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Hanson, Kyle M.; Eudy, Steve L.; Ritzdorf, Thomas L.; Wilson, Gregory J.; Woodruff, Daniel J.; Harris, Randy; Weber, Curtis A.; McGlenn, Tim; Anderson, Timothy A.; Bexten, Daniel P., Processing tools, components of processing tools, and method of making and using same for electrochemical processing of microelectronic workpieces.
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Cohen, Uri, Seed layers for metallic interconnects.
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Cohen,Uri, Seed layers for metallic interconnects.
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Cohen, Uri, Seed layers for metallic interconnects and products.
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Chen, Linlin; Graham, Lyndon W.; Ritzdorf, Thomas L.; Fulton, Dakin; Batz, Jr., Robert W., Submicron metallization using electrochemical deposition.
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Hongo, Akihisa; Nagai, Mizuki; Ohno, Kanji; Kimizuka, Ryoichi; Maruyama, Megumi, Substrate plating method and apparatus.
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Wilson, Gregory J.; McHugh, Paul R.; Hanson, Kyle M., System for electrochemically processing a workpiece.
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Wilson, Gregory J.; McHugh, Paul R.; Hanson, Kyle M., System for electrochemically processing a workpiece.
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Wilson,Gregory J.; McHugh,Paul R.; Weaver,Robert A.; Ritzdorf,Thomas L., Tuning electrodes used in a reactor for electrochemically processing a microelectronic workpiece.
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Wilson,Gregory J.; McHugh,Paul R.; Weaver,Robert A.; Ritzdorf,Thomas L., Tuning electrodes used in a reactor for electrochemically processing a microelectronic workpiece.
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Wilson,Gregory J.; McHugh,Paul R.; Weaver,Robert A.; Ritzdorf,Thomas L., Turning electrodes used in a reactor for electrochemically processing a microelectronic workpiece.
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Wilson, Gregory J.; McHugh, Paul R.; Hanson, Kyle M., Workpiece processor having processing chamber with improved processing fluid flow.
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Wilson,Gregory J.; McHugh,Paul R.; Hanson,Kyle M., Workpiece processor having processing chamber with improved processing fluid flow.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Method for forming capped copper electrical interconnects 원문보기

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Method for forming capped copper electrical interconnects 원문보기

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연구과제 타임라인

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