이 특허를 인용한 특허 (87)

1. Borkovic, Drazen; McElvain, Kenneth S., Analysis of digital circuits with time division multiplexing.

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2. Genetti, Wayne Andrew; Sotak, David George, Apparatus for verification of IC mask sets.

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3. Or-Bach, Zvi, Array of programmable cells with customized interconnections.

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4. Betz, Vaughn; Rose, Jonathan, Automatic generation of programmable logic device architectures.

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5. Betz,Vaughn; Rose,Jonathan, Automatic generation of programmable logic device architectures.

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6. Baxter Glenn A. ; Buch Kiran B. ; Pang Raymond C. ; Law Edwin S., Boundary scan chain with dedicated programmable routing.

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7. Souef, Laurent; Bombal, Jerome; Ginetti, Bernard, Computer implemented circuit synthesis system.

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8. Or Bach,Zvi, Customizable and programmable cell array.

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9. Or Bach,Zvi, Customizable and programmable cell array.

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10. Or Bach,Zvi, Customizable and programmable cell array.

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11. Or-Bach Zvi ; Wurman Ze'ev ; Zeman Richard ; Cooke Laurance, Customizable and programmable cell array.

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12. Or-Bach, Zvi, Customizable and programmable cell array.

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13. Or-Bach, Zvi, Customizable and programmable cell array.

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14. Or-Bach, Zvi; Wurman, Ze'ev; Zeman, Richard; Cooke, Laurance, Customizable and programmable cell array.

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15. Souef Laurent,FRX ; Bombal Jerome,FRX ; Ginetti Bernard,FRX, Design for test area optimization algorithm.

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16. Chesal, Ian; Borer, Terry, Directed design space exploration.

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17. Beal Samuel W. ; Kaptonoglu Sinan ; Lien Jung-Cheun ; Shu William ; Chan King W. ; Plants William C., Enhanced field programmable gate array.

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18. McGowan John E., Field programmable gate array with mask programmed analog function circuits.

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19. John E. McGowan, Field programmable gate array with mask programmed input and output buffers.

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20. McGowan John E., Field programmable gate array with mask programmed input and output buffers.

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21. Weingartner Thomas A. ; Short Paul J. ; Espelien Mark A. ; Woods Jordon W., Fully programmable and configurable application specific integrated circuit.

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22. Law Edwin S. ; Buch Kiran B. ; Baxter Glenn A. ; Pang Raymond C., Hardwire logic device emulating an FPGA.

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23. Edwin S. Law ; Kiran B. Buch ; Glenn A. Baxter ; Raymond C. Pang, Hardwire logic device emulating any of two or more FPGAs.

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24. Charles N. Choukalos ; Alvar Antonio Dean ; Scott Alan Tetreault ; Sebastian Theodore Ventrone, High level automatic core configuration.

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25. Goetting F. Erich ; Frake Scott O. ; Kondapalli Venu M., Input/output buffer supporting multiple I/O standards.

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26. Fang,Hsin Wo; Ho,Ming Jing, Input/output circuits with programmable option and related method.

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27. Or-Bach Zvi, Integrated circuit device.

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28. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.

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29. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.

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30. Or-Bach Zvi, Integrated circuits which employ look up tables to provide highly efficient logic cells and logic functionalities.

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31. Kaneko, Yoshio; Tomishima, Atsushi, Interchangeable FPGA-gate array.

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32. Bednar, Thomas R.; Dunn, Paul E.; Gould, Scott W.; Panner, Jeannie H.; Zuchowski, Paul S., Macro design techniques to accommodate chip level wiring and circuit placement across the macro.

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33. Bednar, Thomas R.; Dunn, Paul E.; Gould, Scott W.; Panner, Jeannie H.; Zuchowski, Paul S., Macro design techniques to accommodate chip level wiring and circuit placement across the macro.

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34. Bednar,Thomas R.; Dunn,Paul E.; Gould,Scott W.; Panner,Jeannie H.; Zuchowski,Paul S., Macro design techniques to accommodate chip level wiring and circuit placement across the macro.

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35. Park, Jonathan, Mask-programmable logic devices with programmable gate array sites.

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36. Forrest H. Bennett, III ; John R. Koza, Method and apparatus for automatic synthesis, placement and routing of complex structures.

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37. How, Dana; Srinivasan, Adi; Osann, Jr., Robert; Mukund, Shridhar, Method and apparatus for controlling and observing data in a logic block-based ASIC.

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38. How Dana ; Srinivasan Adi ; Osann Robert ; Mukund Shridhar, Method and apparatus for controlling and observing data in a logic block-based asic.

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39. Shenoy,Narendra V.; Kawa,Jamil; Camposano,Raul, Method and apparatus for designing an integrated circuit using a mask-programmable fabric.

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40. Borkovic, Drazen; McElvain, Kenneth S., Method and apparatus for the design and analysis of digital circuits with time division multiplexing.

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41. Raza S. Babar, Method and apparatus to generate mask programmable device.

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42. Raza S. Babar, Method and apparatus to generate mask programmable device.

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43. Raza S. Babar, Method and apparatus to generate mask programmable device.

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44. Asaad, Sameh W; Bellofatto, Ralph E; Brezzo, Bernard; Haymes, Charles L; Kapur, Mohit; Parker, Benjamin D; Roewer, Thomas; Tierno, Jose A, Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs).

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45. Yin Patrick, Method and system for allowing an integrated circuit to be portably generated from one manufacturing process to another.

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46. Baxter, Glenn A., Method for controlling timing in reduced programmable logic devices.

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47. Glenn A. Baxter, Method for converting programmable logic devices into standard cell devices.

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48. Or-Bach Zvi, Method for design and manufacture of semiconductors.

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49. Or-Bach, Zvi, Method for design and manufacture of semiconductors.

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50. Gore,Brooklin J.; Lee,Michael D.; Priest,Matthew L., Method for determining a matched routing arrangement for semiconductor devices.

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51. Baxter, Glenn A., Method for improving area in reduced programmable logic devices.

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52. Baxter, Glenn A., Method for managing database models for reduced programmable logic device components.

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53. Perry, Steven; Nixon, Gregor; Kong, Larry; Scott, Alasdair; Hall, Andrew; Wang, Lingli; Dettmar, Chris; Park, Jonathan; Price, Richard, Method for programming a mask-programmable logic device and device so programmed.

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54. Perry,Steven; Nixon,Gregor; Kong,Larry; Scott,Alasdair; Hall,Andrew; Wang,Lingli; Dettmar,Chris; Park,Jonathan; Price,Richard, Method for programming a mask-programmable logic device and device so programmed.

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55. Vashi Mehul ; Buch Kiran, Method for verifying timing in a hard-wired IC device modeled from an FPGA.

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56. Vashi, Mehul; Buch, Kiran, Method for verifying timing in a hard-wired IC device modeled from an FPGA.

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57. Bombal, Jerome; Souef, Laurent, Method of discriminating between different types of scan failures, computer readable code to cause a display to graphically depict one or more simulated scan output data sets versus time and a comput.

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58. Baxter Glenn A. ; Buch Kiran B. ; Pang Raymond C. ; Law Edwin S., Method of implementing a boundary scan chain.

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59. Bueti, Serafino; Goodnow, Kenneth J.; Mann, Gregory J.; Norman, Jason M., Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry.

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60. Chun-Chih Yang TW; Yung-Chung Chang TW; Shu-Tzu Wang TW, Method of placement and routing for an array device.

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61. Genetti,Wayne Andrew; Sotak,David George, Method of verifying IC mask sets.

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62. Walstrum, Jr., James A., Method to reduce configuration solution using masked-ROM.

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63. Li, Mu-Jing, Method, system and computer product to produce a computer-generated integrated circuit design.

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64. Chung-Hsing Wang TW, Methodology for generating a design rule check notch-error free core cell library layout.

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65. McElvain, Kenneth S.; Erickson, Robert, Methods and apparatuses for designing integrated circuits.

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66. McElvain,Kenneth S.; Erickson,Robert, Methods and apparatuses for designing integrated circuits.

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67. Gloster, Clay S.; Gay, Wanda D.; Amoo, Michaela E., Multiple-memory application-specific digital signal processor.

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68. Baxter Glenn A. ; Buch Kiran B. ; Law Edwin S., Programmable I/O cell with dual boundary scan.

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69. Baxter Glenn A. ; Buch Kiran B. ; Law Edwin S., Programmable IC with gate array core and boundary scan capability.

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70. Pileggi, Larry; Schmit, Herman, Programmable gate array based on configurable metal interconnect vias.

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71. Baxter, Glenn A., Programmable logic device structures in standard cell devices.

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72. Baxter, Glenn A., Programmable logic device structures in standard cell devices.

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73. Baxter,Glenn A., Programmable logic device structures in standard cell devices.

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74. Lien,Scott Te Sheng, Programmable logic device-structured application specific integrated circuit.

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75. Or-Bach Zvi, Semiconductor device.

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76. Or-Bach Zvi ; Cox Bill Douglas, Semiconductor device.

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77. Zvi Or-Bach ; Bill Douglas Cox, Semiconductor device.

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78. Baxter Glenn A., System and method for generating memory initialization logic in a target device with memory initialization bits from a programmable logic device.

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79. Iadanza Joseph A. ; Kilmoyer Ralph D., System and method for improved bitwrite capability in a field programmable memory array.

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80. Sanders, Lester S., System and method for translating a report file of one logic device to a constraints file of another logic device.

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81. Borer, Terry; Chesal, Ian; Schleicher, James; Mendel, David; Hutton, Mike; Ratchev, Boris; Sankar, Yaska; van Antwerpen, Babette; Baeckler, Gregg; Yuan, Richard; Brown, Stephen; Betz, Vaughn; Chan, Kevin, Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage.

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82. Borer,Terry; Chesal,Ian; Schleicher,James; Mendel,David; Hutton,Mike; Ratchev,Boris; Sankar,Yaska; van Antwerpen,Babette; Baeckler,Gregg; Yuan,Richard; Brown,Stephen; Betz,Vaughn; Chan,Kevin, Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage.

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83. Padalia, Ketan; Bozman, Kimberly; Betz, Vaughn, Techniques for grouping circuit elements into logic blocks.

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84. Padalia,Ketan; Bozman,Kimberly; Betz,Vaughn, Techniques for grouping circuit elements into logic blocks.

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85. Yu Meng-Lin ; Subrahmanyam P. A., Timed circuit simulation in hardware using FPGAs.

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86. Scott,Alasdair; Nixon,Gregor, Timing analysis for programmable logic.

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87. Singh, Gagandeep; Gandhi, Pawan Deep, Using smart timing models for gate level timing simulation.

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