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Method and system for creating and validating low level description of electronic design from higher level, behavior-ori

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0077403 (1993-06-14)
발명자 / 주소
  • Dangelo Carlos (Los Gatos CA) Deeley Richard (San Jose CA) Nagasamy Vijay (Union City CA) Vafai Manoucher (Los Gatos CA)
출원인 / 주소
  • LSI Logic Corporation (Milpitas CA 02)
인용정보 피인용 횟수 : 101  인용 특허 : 0

초록

A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications using a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essenti

대표청구항

A method of synthesizing an electronic design, comprising: creating a matrix of milestones, the matrix having columns representing levels of design abstraction and rows representing stages of design development; providing at least one activity associated with each milestone, wherein completion of th

이 특허를 인용한 특허 (101)

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