초록 ▼

A multiprocessor programmable interrupt controller system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt request (IRQ) related messages. Each processor chip has an on-board interrupt acceptance unit (IAU) coupled to the interrupt bus to accept IRQs and to broadca

A multiprocessor programmable interrupt controller system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt request (IRQ) related messages. Each processor chip has an on-board interrupt acceptance unit (IAU) coupled to the interrupt bus to accept IRQs and to broadcast IRQs that it generates. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus to broadcast I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two wires for data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to this procedure also provides uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done via the system bus. IAU acceptance logic is minimized by allowing retry of a delivered message when the acceptance latches are full. The increase in interrupt bus traffic due to retry is minimized by controlling the time intervals between rebroadcasts of unaccepted IRQs. Exponential timers control this interval so that each succeeding interval is a multiplicative factor, typically 2, greater than the preceding interval.

대표청구항 ▼

A method for controlling interrupt request traffic in a multiprocessor interrupt controller system having an interrupt bus for broadcasting interrupt request and acceptance messages, two or more interrupt acceptance agents, each coupled to the interrupt bus and to an associated processor for broadca

A method for controlling interrupt request traffic in a multiprocessor interrupt controller system having an interrupt bus for broadcasting interrupt request and acceptance messages, two or more interrupt acceptance agents, each coupled to the interrupt bus and to an associated processor for broadcasting interprocessor interrupt request messages initiated by an associated processor and for receiving interprocessor interrupt requests that are broadcast on the interrupt bus and broadcasting an acceptance message for interrupt request messages that are accepted by an interrupt acceptance agent, the method comprising the following step: a) accepting an interprocesor interrupt request message from its associated processor; b) boadcasting the interrupt request message on the interrupt bus; c) monitoring the interrupt bus for an acceptance message indicating that the interrupt request has been accepted by an interrupt acceptance agent; d) clearing the interrupt request message if an acceptance message is received, otherwise proceed to step e); e) broadcasting the interrupt at intervals of time until the interrupt request message is accepted, the intervals increasing exponentially by a constant multiplicative factor greater than one after each broadcast; f) counting the number of times a same interrupt request message has been broadcast; g) comparing the count number with a prescribed threshold number which, if exceeded, causes a system status flag to be asserted; and h) returning to step c).