초록 ▼

A multi-master digital computer system has a bus, a plurality of master devices connected to the bus, a plurality of slave devices connected to the bus, and a bus controller for arbitrating bus requests by the master devices and for granting the bus to a selected one of the plurality of the master d

A multi-master digital computer system has a bus, a plurality of master devices connected to the bus, a plurality of slave devices connected to the bus, and a bus controller for arbitrating bus requests by the master devices and for granting the bus to a selected one of the plurality of the master devices. Each master device is capable of originating a bus cycle to transmit data to or receive data from a desired slave device. The bus controller grants the bus to a selected master device which enters an address master state and addresses the desired slave device. The selected master device is transferred to a bus master state where a data transfer to or from the slave device is initiated. The selected master device then transfers to a data master state unless the selected master device wants, and is permitted through an arbiter, to retain control of the bus. The bus controller grants a bus request to a requesting master device through to the arbiter. The requesting master device is transferred into the address master state while the selected master device is still in the data master state, thus performing a pipelining operation.

대표청구항 ▼

A multi-master digital computer system, comprising: (a) a bus having separate address lines and data lines; (b) at least first and second master device means connected to the bus for originating bus cycles, each having means for requesting the bus and each having means for releasing the bus, each ha

A multi-master digital computer system, comprising: (a) a bus having separate address lines and data lines; (b) at least first and second master device means connected to the bus for originating bus cycles, each having means for requesting the bus and each having means for releasing the bus, each having addressing means activated during a bus cycle and during an address master state, and each having data means for transmitting information during a subsequent data master state; (c) at least one slave device means connected to the bus, addressable by the first and second master device means during their respective address master states for receiving or transmitting data during their respective data master states; and (d) an arbiter for arbitrating bus requests by the first and second master device means during the bus cycle, for granting both the address and data lines of the bus to a selected one of the first and second master device means for transmitting to, or receiving data from, the slave device means and for granting only the address lines of the bus to the other master device means to enter the address master state upon its requesting the bus, while the selected master device means is coupled to only the data lines of the bus in the data master state, the arbiter capable of granting the address lines and the data lines separately, thereby accelerating the transfer of the bus from the selected master device means to the other master device means in a pipelining manner.