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A method applicable to a host computer system having a system bus connected to a CPU, and a PCMCIA controller having status registers, means for supplying back off signals to the CPU and line buffers capable of being in a normal and high impedance state. A multi pin connector is located in each card

A method applicable to a host computer system having a system bus connected to a CPU, and a PCMCIA controller having status registers, means for supplying back off signals to the CPU and line buffers capable of being in a normal and high impedance state. A multi pin connector is located in each card socket and connected to a line buffer. Each connector has common address, data and control pins, power pins, ground pins longer than the data pins and card detect signal pins shorter than the signal pins. The first step is to detect the commencement of an insertion or removal of a PCMCIA card to or from a socket by monitoring the ground and card detect signal pins. After detection, commence termination of all CPU usage of common address, data and control lines by asserting a back off signal. Next, determine if the usage is terminated by monitoring the status registers in the controller. Next, place the common address, data and control lines in a high impedance state. Next, detect that the PC card has been completely inserted or removed by monitoring the ground pins or the card detect signal pins. Next, apply power to the PCMCIA card socket. After a delay return the common address, data and control lines to their normal operating impedance level.

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In a method of operating a host computer system having at least a system bus which is connected to a CPU, a system memory and a controller having status registers and means for supplying back off signals indicating that new tasks cannot be accepted to the CPU and a plurality of line buffers capable

In a method of operating a host computer system having at least a system bus which is connected to a CPU, a system memory and a controller having status registers and means for supplying back off signals indicating that new tasks cannot be accepted to the CPU and a plurality of line buffers capable of being in a normal and high impedance state, and a plurality of add in PC card sockets for receiving PC cards connected to said controller, said sockets each having a multi pin connector that includes common address, data and control lines as well as power, ground and card detect signal pins connected to said line buffers, the steps comprising: detecting the commencement of the removal of a PC card from a PC card socket; upon detection of said commencement of said removal of a PC card from a socket, commencing orderly termination of all usage by said CPU of said common address, data and control lines; determining that all usage by said CPU of said common address, data an control lines is complete; placing said common address, data and control lines in a high impedance state; detecting the completion of said removal of said PC card into a PC card socket; and upon detecting the completion of said removal of said PC card into a PC card socket, returning said common address, data and control lines to their normal operating impedance level.