초록 ▼

The data compression device allows detection of signals of diverse wave forms and also recording of the time and number of their next appearance. In particular, the Information Compressor includes an analog-to-digital converter with a data processor connected to it. A controller is interconnected to

The data compression device allows detection of signals of diverse wave forms and also recording of the time and number of their next appearance. In particular, the Information Compressor includes an analog-to-digital converter with a data processor connected to it. A controller is interconnected to the data processors and also to the analog to digital converter. A signal detector may be interconnected with the data processes and the analog-to-digital converter and it is also preferable for a control console to be provided.

대표청구항 ▼

An information compressor, comprising: an analog-to-digital converter with an input constituting the input of said compressor, a data output, and a control output; multiple data processors with first data inputs, address inputs, first control inputs, second control inputs, and first and second outpu

An information compressor, comprising: an analog-to-digital converter with an input constituting the input of said compressor, a data output, and a control output; multiple data processors with first data inputs, address inputs, first control inputs, second control inputs, and first and second outputs; with the first data inputs connected to said data output of said analog-to-digital converter, first control inputs connected to said control output of said analog-to-digital converter, and first and second outputs constituting first and second outputs of the compressor; and a controller with a control input, a first input, an output, and an address output; with the control input connected to said control output of said analog-to-digital converter, the first input connected to said second outputs of said data processors, the output connected to said second control inputs of said data processors, and the address output connected to said address inputs of said data processors; wherein each data processor comprises: an individual working memory; a comparator with the following elements, inputs, and outputs: a data input and a first input which constitute said data input and said second input of said data processor, a second input, and outputs, wherein said comparator comprises a first adder having first and second inputs constituting said data input and said second input of said comparator, a first output, and a second output constituting one of said outputs of said comparator; a second adder having a first input connected to said first output of said first adder, a second input, and an output constituting one of said outputs of said comparator; and a multiplexer having a first input connected to said second output of said first adder, a second input constituting said first input of said comparator and an output connected to said second input of said second adder; said working memory having a data input, an address input, a first input, a second input, a first output, and a second output; with said first input constituting said data input, said address input, and said first control input of said data processor, said first output constituting said first output of said data processor and connected to said second input of said comparator; a control circuit with the following inputs and outputs: first and second inputs connected to said outputs of said comparator, third and fourth inputs constituting said second control input and said first input of said data processor, a fifth input connected to said second output of said working memory, a sixth input constituting said first control input of said data processor, a first output connected to said second input of said working memory, and an output; and a read only memory having an input connected to said first output of said control circuit and an output constituting said second output of said data processor.