이 특허를 인용한 특허 (100)

1. Alverson, Gail A.; Callahan, II, Charles David; Kahan, Simon H.; Koblenz, Brian D.; Porterfield, Allan; Smith, Burton J., Accessing a collection of data items in a multithreaded environment.

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2. Gilgen, David B.; Tuel, Anthony R., Adaptively processing client requests to a network server.

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3. Gilgen, David B; Tuel, Anthony R, Adaptively processing client requests to a network server.

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4. Pratt Steven L. ; Rafanello Benedict M., Advanced method for checking the integrity of node-based file systems.

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5. Freund Thomas,GBX ; Holdsworth Simon Antony James,GBX ; Houston Iain Stuart Caldwell,GBX, Apparatus and method for dispatching client method calls within a server computer system.

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6. Godtland, Paul LuVerne; Timms, Jr., George David, Apparatus and method for providing simultaneous local and global addressing with hardware address translation.

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7. Beckman, Brian C.; Andrews, Anthony D.; Armanasu, Alexander A., Automatic object caller chain with declarative impersonation and transitive trust.

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8. Brian C. Beckman ; Anthony D. Andrews ; Alexander A. Armanasu, Automatic object caller chain with declarative impersonation and transitive trust.

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9. Kling, Lars-Orjan; Johnson, Sten Edvard; Holmberg, Per Anders; Egeland, Terje, Batch-wise handling of signals in a processing system.

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10. Enokida, Tsutomu, Compiler device and computer-readable recording medium with a compiler recorded therein.

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11. Andrews, Anthony D., Composable roles.

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12. Chopra Gagan ; McCline Matthew Clark ; Helland Patrick James ; Al-Ghosein Mohsen M., Concurrency control of state machines in a computer system using cliques.

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13. Davis, Gordon Taylor; Heddes, Marco C.; Leavens, Ross Boyd; Verplanken, Fabrice Jean, Controller for multiple instruction thread processors.

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14. Davis, Gordon Taylor; Heddes, Marco C.; Leavens, Ross Boyd; Verplanken, Fabrice Jean, Controller for multiple instruction thread processors.

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15. Faanes,Gregory J.; Scott,Steven L.; Lundberg,Eric P.; Moore, Jr.,William T.; Johnson,Timothy J., Decoupled scalar/vector computer architecture system and method.

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16. Scott, Steven L.; Faanes, Gregory J., Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system.

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17. Alverson, Gail A.; Callahan, II, Charles David; Kahan, Simon H.; Koblenz, Brian D.; Porterfield, Allan; Smith, Burton J., Detecting access to a memory location in a multithreaded environment.

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18. Dietterich, Daniel J.; Phillips, Robert S.; Carter, John B.; Davis, Scott H.; Frank, Steven J.; Abraham, William, Dynamic directory service.

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19. Alferness Merwin H. ; Caldarale Charles R. ; Johnson David C. ; Johnson David R. ; McBreen James R. ; Ward Wayne D., Enqueue instruction in a system architecture for improved message passing and process synchronization.

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20. Dubey Pradeep Kumar ; Barton Charles Marshall ; Chuang Chiao-Mei ; Lam Linh Hue ; O'Brien John Kevin ; O'Brien Kathryn Mary, Executing speculative parallel instructions threads with forking and inter-thread communication.

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21. Kohn,James R., Indirectly addressed vector load-operate-store method and apparatus.

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22. Phillips,Robert S.; Davis,Scott H.; Dietterich,Daniel J.; Nyman,Scott E.; Porter,David, Internet-based shared file service with native PC client access and semantics.

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23. Phillips,Robert S.; Davis,Scott H.; Dietterich,Daniel J.; Nyman,Scott E.; Porter,David, Internet-based shared file service with native PC client access and semantics and distributed access control.

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24. Ohsawa, Taku; Matsushita, Satoshi, Interprocessor register succession method and device therefor.

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25. Saville Winthrop L. ; Ross Kevin, Interrupt-controlled thread processing.

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26. Brown,Michael Wayne; Garfinkle,Scott E.; Paolini,Michael A.; Wendt,David Mark, Language extension for light weight threading in a JVM.

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27. Scott, Steven L., Latency tolerant distributed shared memory multiprocessor computer.

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28. Thiyagarajan,Murali, Linear instance mapping for query rewrite.

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29. Pautsch, Gregory W.; Pautsch, Adam, Method and apparatus for cooling electronic components.

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30. Kohn, James R., Method and apparatus for indirectly addressed vector load-add-store across multi-processors.

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31. Kohn,James R., Method and apparatus for indirectly addressed vector load-add-store across multi-processors.

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32. Moyer William C. ; Arends John ; Scott Jeffrey W., Method and apparatus for interfacing a processor to a coprocessor.

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33. Moyer,William C.; Arends,John; Scott,Jeffrey W., Method and apparatus for interfacing a processor to a coprocessor.

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34. Bender,Ernest S.; Yee,Chun Kwan K., Method and apparatus for managing thread execution in a multithread application.

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35. Wyatt,David A.; Sreenivas,Aditya, Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device.

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36. Carlson, Richard, Method and apparatus for translation lookaside buffers to access a common hardware page walker.

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37. Nguyen Khoa ; Sarkar Vivek, Method and system for generating compact code for the loop unrolling transformation.

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38. Williams Antonty S. ; Mitchell Alexander A. ; Atkinson Robert G. ; Hodges C. Douglas ; Posch Johann ; Wittenberg Craig H., Method and system for multi-threaded processing.

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39. Williams, Antonty S.; Mitchell, Alexander A.; Atkinson, Robert G.; Hodges, C. Douglas; Posch, Johann; Wittenberg, Craig H, Method and system for multi-threaded processing.

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40. Fussell, David K., Method for managing message flow in a multithreaded, message flow environment.

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41. Fussell,David K., Method, apparatus and computer program product for managing message flow in a multithreaded, message flow environment.

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42. Luis F. Stevens, Method, system and computer program product for managing memory in a non-uniform memory access system.

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43. Stevens Luis F., Method, system and computer program product for managing memory in a non-uniform memory access system.

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44. Stevens Luis F., Method, system and computer program product for managing memory in a non-uniform memory access system.

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45. Richardson John L., Method, system and computer program product for profiling thread virtual memory accesses.

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46. Richardson John L. ; Stevens Luis, Method, system, and computer program product for allocating physical memory in a distributed shared memory network.

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47. Stevens Luis F. ; Subramanya Bhanu, Method, system, and computer program product for page replication in a non-uniform memory access system.

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48. Matz,Paul E.; Okita,Glen K.; Chahrouri,Gebran; Butensky,Michael, Methods and apparatus for executing a transaction task within a transaction processing system employing symmetric multiprocessors.

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49. Ohsawa,Taku; Matsushita,Satoshi, Multi-thread executing method and parallel processing system.

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50. Dennis,Jack B.; Sandbote,Sam B., Multi-thread peripheral processing using dedicated peripheral bus.

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51. Helland, Patrick James; Limprecht, Rodney; Al-Ghosein, Mohsen; Reed, David R., Multi-user server application architecture with single-user object tier.

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52. Holmberg, Per Anders; Egeland, Terje; Linnermark, Nils Ola; Strombergson, Karl Oscar Joachim; Carlsson, Magnus, Multiple job signals per processing unit in a multiprocessing system.

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53. Scott,Steven L.; Faanes,Gregory J.; Stephenson,Brick; Moore, Jr.,William T.; Kohn,James R., Multistream processing memory-and barrier-synchronization method and apparatus.

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54. Gosior,Jason; Broughton,Colin; Jacobsen,Phillip; Sobota,John, Multithread embedded processor with input/output capability.

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55. Cismas, Sorin C., Multithreaded data/context flow processing architecture.

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56. Frigo, Matteo; Gheith, Ahmed; Strumpen, Volker, Multithreaded processor architecture with operational latency hiding.

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57. Frigo, Matteo; Gheith, Ahmed; Strumpen, Volker, Multithreaded processor architecture with operational latency hiding.

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58. Osborne Randy B., Network interface having support for allowing remote operations with reply that bypass host computer interaction.

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59. Osborne Randy B., Network interface having support for message processing and an interface to a message coprocessor.

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60. Picazo ; Jr. Jose J. ; Lee Paul Kakul ; Zager Robert P., Network packet switch using shared memory for repeating and bridging packets at media rate.

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61. Davis,Gordon Taylor; Heddes,Marco C.; Leavens,Ross Boyd; Verplanken,Fabrice Jean, Network processor which makes thread execution control decisions based on latency event lengths.

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62. Scott,Steven L.; Dickson,Chris; Reinhardt,Steve, Node translation and protection in a clustered multiprocessor system.

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63. Hinson, Gerald L.; Al-Ghosein, Mohsen; Dumitru, Donald W.; McCrady, Donald J.; Pollack, Seth B.; Swartz, Stephen T., Object connectivity through loosely coupled publish and subscribe events.

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64. Hinson,Gerald L.; Al Ghosein,Mohsen M.; Dumitru,Donald W.; McCrady,Donald J.; Pollack,Seth B.; Swartz,Stephen T., Object connectivity through loosely coupled publish and subscribe events.

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65. Hinson,Gerald L.; Al Ghosein,Mohsen M.; Dumitru,Donald W.; McCrady,Donald J.; Pollack,Seth B.; Swartz,Stephen T., Object connectivity through loosely coupled publish and subscribe events.

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66. Hinson, Gerald L.; McCrady, Donald J.; Swartz, Stephen T., Object connectivity through loosely coupled publish and subscribe events with filtering.

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67. Andrews, Anthony D.; Thatte, Satish R.; Hill, Richard D.; Norlander, Rebecca A.; Armanasu, Alexander A., Object security boundaries.

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68. Anthony D. Andrews ; Satish R. Thatte ; Richard D. Hill ; Rebecca A. Norlander ; Alexander A. Armanasu, Object security boundaries.

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69. Goto Masaru,JPX, One-chip microcomputer including RISC processor and one or more coprocessors having control registers mapped as internal registers for the RISC processor.

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70. Lakhotia, Arun; Karim, Md. Enamul; Walenstein, Andrew, Phylogeny generation.

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71. Dennis, Jack B., Prioritizing resource utilization in multi-thread computing system.

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72. Boudou Alain,FRX ; Derne Henriette,FRX, Process for transferring data between nodes in a multinodal information system.

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73. Georgiou, Christos John; Denneau, Monty Montague, Programmable network protocol handler architecture.

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74. Georgiou,Christos J.; Denneau,Monty M.; Salapura,Valentina; Bunce,Robert M., Programmable network protocol handler architecture.

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75. Dievendorff, Richard; Helland, Patrick J.; Chopra, Gagan; Al Ghosein, Mohsen M., Queued component interface passing for results outflow from queued method invocations.

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76. Richard Dievendorff ; Patrick J. Helland ; Gagan Chopra ; Mohsen Al-Ghosein, Queued method invocations on distributed component applications.

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77. Goto Masaru,JPX, RISC type microprocessor and information processing apparatus.

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78. Scott, Steven L.; Faanes, Gregory J.; Stephenson, Brick; Moore, Jr., William T.; Kohn, James R., Relaxed memory consistency model.

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79. Carter John B. ; Davis Scott H. ; Frank Steven J., Remote access and geographically distributed computers in a globally addressable storage environment.

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80. Scott, Steven L.; Dickson, Chris; Fromm, Eric C.; Anderson, Michael L., Remote address translation in a multiprocessor system.

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81. Scott, Steven L., Remote translation mechanism for a multi-node system.

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82. Sheets, Kitrick; Hastings, Andrew B., Remote translation mechanism for a multinode system.

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83. Alverson,Gail A.; Callahan, II,Charles David; Kahan,Simon H.; Koblenz,Brian D.; Porterfield,Allan; Smith,Burton J., Restricting access to memory in a multithreaded environment.

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84. Klausler, Peter M., Scheduling synchronization of programs running as streams on multiple processors.

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85. Sheets,Kitrick; Williams,Josh; Gettler,Jonathan; Piatz,Steve; Hastings,Andrew B.; Hill,Peter; Bravatto,James G.; Kohn,James R.; Titus,Greg, Scheduling synchronization of programs running as streams on multiple processors.

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86. Sheets, Kitrick, Sharing memory within an application using scalable hardware resources.

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87. Russell,Wilfred G.; Helland,Patrick J.; Hope,Greg; Limprecht,Rodney; Al Ghosein,Mohsen M.; Gray,Jan S., Software component execution management using context objects for tracking externally-defined intrinsic properties of executing software components within an execution environment.

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88. Russell,Wilfred G.; Helland,Patrick James; Hope,Greg; Limprecht,Rodney; Al Ghosein,Mohsen; Gray,Jan Stephen, Software component execution management using context objects for tracking externally-defined intrinsic properties of executing software components within an execution environment.

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89. Davis Scott H. ; Carter John B. ; Frank Steven J. ; Lee Hsin H. ; Dietterich Daniel J., Structured data storage using globally addressable memory.

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90. Shailender Chaudhry ; Marc Tremblay, Supporting multi-dimensional space-time computing through object versioning.

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91. Grohoski,Gregory F.; Olson,Christopher H., Synchronization primitives for flexible scheduling of functional unit operations.

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92. Alverson,Gail A.; Callahan, II,Charles David; Kahan,Simon H.; Koblenz,Brian D.; Porterfield,Allan; Smith,Burton J., Synchronization techniques in a multithreaded environment.

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93. McCue, Kevin C., System and method for dynamic allocation of software resources.

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94. Harpur, Liam; O'Sullivan, Patrick J.; Stern, Edith H.; Willner, Barry E., System and method for motivating delayed responses to messages.

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95. McCormick, Jr., James Earl, System and method for out-of-order prefetch instructions in an in-order pipeline.

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96. Faanes, Gregory J.; Lundberg, Eric P.; Scott, Steven L.; Baird, Robert J., System and method for processing memory instructions using a forced order queue.

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97. Carter John B. ; Davis Scott H. ; Dietterich Daniel J. ; Frank Steven J. ; Phillips Robert S. ; Woods John ; Porter David ; Lee Hsin H., System and method for providing highly available data storage using globally addressable memory.

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98. Joy William N., System and method for space efficient object locking using global and local locks.

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99. Dice David ; Mann Ronald J. ; Vandette Robert G., System and method for synchronizing access to shared variables in a virtual machine in a digital computer system.

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100. Tuel, Jr., William G.; Govindaraju, Rama K., Thread dispatcher for multi-threaded communication library.

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