초록 ▼

A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a bottom electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes

A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a bottom electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used formation of the underlying integrated circuit.

대표청구항 ▼

A capacitor structure for an integrated circuit, the integrated circuit comprising active devices formed on a semiconductor substrate, overlying layers comprising interconnect metallization, a top dielectric layer having bond pad openings formed through the dielectric for contacting the underlying i

A capacitor structure for an integrated circuit, the integrated circuit comprising active devices formed on a semiconductor substrate, overlying layers comprising interconnect metallization, a top dielectric layer having bond pad openings formed through the dielectric for contacting the underlying interconnect metallization, and a surface passivation layer formed over the integrated circuit, the capacitor structure formed on a surface of the passivation layer, comprising: a plurality of vias defined through the passivation layer and the top dielectric layer; a first conductive layer defining a first capacitor electrode extending over the surface of the passivation layer and contacting the underlying interconnect metallization through at least one of the plurality of vias; a layer of capacitor dielectric formed on the first capacitor electrode; a second conductive layer formed on the capacitor dielectric and overlying the first electrode and defining a top capacitor electrode, part of the second conductive layer extending laterally of the first electrode over the surface of the passivation layer and contacting the underlying interconnect metallization through another of the plurality of vias; thereby routing interconnections from each of the electrodes of the capacitor to the interconnect metallization of the underlying integrated circuit through the passivation layer underneath the conductive layers forming the capacitor structure.