초록 ▼

An information processing network includes multiple processing devices, a main storage memory, and an interface coupling the processing devices to the main storage memory. All processing devices contend for control of the interface on an equal basis, subject to a dynamically shifting sequence of pri

An information processing network includes multiple processing devices, a main storage memory, and an interface coupling the processing devices to the main storage memory. All processing devices contend for control of the interface on an equal basis, subject to a dynamically shifting sequence of priority rankings, invoked to resolve contentions for the interface or for one of a plurality of hardware class locks. The class locks are uniquely associated with different capabilities or classes of data operations, which reduces the number of contentions and allows multiple operations to proceed simultaneously. Arbitration logic encompassing all of the processing devices is duplicated in each of the processing devices, and kept coherent through an interconnection of multiple data buses. One bus is associated with each processing device, receives the output of the associated processing device and provides the output to each of the other processing devices. A lock sequencer includes a store-tracking feature that minimizes the time that any processor, after losing a contention for a lock, is in a hold condition.

대표청구항 ▼

An information processing network including: a plurality of processing devices for executing computer program instructions to manipulate bid-encoded data, and a shared interface connected to the processing devices for allowing transmission of the bit-encoded data between each of the processing devic

An information processing network including: a plurality of processing devices for executing computer program instructions to manipulate bid-encoded data, and a shared interface connected to the processing devices for allowing transmission of the bit-encoded data between each of the processing devices and the shared interface; wherein each of the processing devices includes an arbitration sector containing arbitration logic for determining a priority among all of the processing devices for access to and control of the shared interface, said arbitration sectors being substantially identical to one another, and; an interconnection means directly coupling all of the arbitration sectors to one another independently of the shared interface for transmitting the arbitration logic among all of the arbitration sectors to maintain coherency of the arbitration logic in all of the arbitration sectors, said interconnection means including a number of said arbitration data busses is equal to the number of the processing devices; and wherein each of the arbitration data busses is uniquely associated with one of the processing devices, in that each arbitration data bus is connected to the arbitration sector of its associated processing device to receive as an input the arbitration logic from the arbitration sector of its associated processing device, each arbitration data bus further being connected to the remaining arbitration sectors of the remaining processing devices to provide the arbitration logic from its associated processing device as an input to the remaining arbitration sectors; and wherein each arbitration sector includes a plurality of arbitration registers, each arbitration register containing information specific to a different one of the processing devices, one of the arbitration registers in each arbitration sector containing arbitration information specific to the particular processing device containing it and providing the arbitration information as an input to an arbitration data bus associated with the particular processing device, each of the remaining arbitration registers of each arbitration sector comprising an input arbitration register for receiving arbitration information as an input from one of the arbitration data busses other than the associated data bus and each said arbitration data bus transmits the arbitration logic only in the direction from its associated processing device to the remaining processing devices; and an interface monitoring register in each arbitration sector for storing logic indicating the priority among the processing devices for control of the shared interface; and a bidirectional data bus connected to the shared interface, and input and output connections between each of the interface monitoring registers and the bidirectional data bus.