$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Process for fabricating an electronic circuit package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/04
출원번호 US-0468313 (1995-06-06)
발명자 / 주소
  • Zalesinski Jerzy M. (Essex Junction VT) Emerick Alan J. (Warren Center PA)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 12  인용 특허 : 14

초록

An electronic circuit package is fabricated by providing a substrate having attached to at least one of its major surfaces, at least one integrated circuit chip; and providing a carrier that comprises a polymeric composition. The carrier holds a desired array of conductive pins, which protrude from

대표청구항

A carrier which comprises a main body portion that contains stand-off portions and holds a desired array of electrically conductive pins protruding from major surfaces thereof; and being fabricated from a polymeric composition; and wherein electrically conductive pins of said array each contain a bu

이 특허에 인용된 특허 (14)

  1. Chang Kin-Shiung (Meriden CT), Assembly of electronic packages by vacuum lamination.
  2. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  3. Hawthorne Emily (San Francisco CA) McCormick John (Redwood City CA), Location and standoff pins for chip on tape.
  4. Gedney ; Ronald Walker ; Rodite ; Robert Richard, Metallized ceramic and printed circuit module.
  5. Ameen Joseph G. (Apalachin NY) Funari Joseph (Vestal NY) Sissenstein ; Jr. David W. (Endwell NY), Mutlilayered flexible circuit package.
  6. Sekiguchi Takeshi (Yokohama JPX) Shiga Nobuo (Yokohama JPX) Aga Keigo (Yokohama JPX), Optical semiconductor device.
  7. Carson ; Kent R. ; Hess ; Charles M., Package for multielement electro-optical devices.
  8. McShane Michael B. (Austin TX) Lin Paul T. (Austin TX) Wilson Howard P. (Austin TX), Packaged semiconductor device having a low cost ceramic PGA package.
  9. Theobald Paul R. (Signal Mountain TN), Plastic chip carrier package.
  10. Hirata Atsuomi (Nara JPX) Mamiya Hirokuni (Yokkaichi JPX), Plastic molded chip carrier package and method of fabricating the same.
  11. Hirata Atsuomi (Nara JPX) Nakamura Yoshihiko (Nishinomiya JPX) Morii Kensaku (Takatsuki JPX), Plastic molded pin grid chip carrier package.
  12. Cohn Charles (Wayne NJ), Plastic pin grid array package.
  13. Darrow Russell E. (Newark Valley NY) Memis Irving (Vestal NY) Poliak Richard M. (Endwell NY), Sealing of integrated circuit modules.
  14. Ogihara Satoru (Hitachi JPX) Numata Shunichi (Hitachi JPX) Miyazaki Kunio (Hitachi JPX) Yokoyama Takashi (Hitachi JPX) Takahashi Ken (Ibaraki JPX) Soga Tasao (Hitachi JPX) Yamada Kazuji (Hitachi JPX), Semiconductor chip module.

이 특허를 인용한 특허 (12)

  1. Yoneda, Yoshiyuki; Tsuji, Kazuto; Orimo, Seiichi; Sakoda, Hideharu; Nomoto, Ryuji; Onodera, Masanori; Kasai, Junichi, Device having resin package and method of producing the same.
  2. Yoneda,Yoshiyuki; Tsuji,Kazuto; Orimo,Seiichi; Sakoda,Hideharu; Nomoto,Ryuji; Onodera,Masanori; Kasai,Junichi, Device having resin package and method of producing the same.
  3. Yoneda Yoshiyuki,JPX ; Tsuji Kazuto,JPX ; Orimo Seiichi,JPX ; Sakoda Hideharu,JPX ; Nomoto Ryuji,JPX ; Onodera Masanori,JPX ; Kasai Junichi,JPX, Device having resin package with projections.
  4. Sirinorakul,Saravuth; Nondhasitthichai,Somchai; Jewjaitham,Sitta, Flat no-lead semiconductor die package including stud terminals.
  5. Tetaka Masafumi,JPX ; Maki Shinichiro,JPX ; Ohyama Nobuo,JPX ; Orimo Seiichi,JPX ; Sakoda Hideharu,JPX ; Yoneda Yoshiyuki,JPX ; Shigeno Akihiro,JPX ; Yokoyama Ryoichi,JPX ; Fujisaki Fumitoshi,JPX ; F, Method and apparatus for fabricating semiconductor device.
  6. Nicholson Dean B. (Windsor CA), Pin grid array solution for microwave multi-chip modules.
  7. Ashiya, Hiroyuki; Suzuki, Masataka; Tanaka, Yoshiyuki; Matsuura, Shingo, Relay device and relay device mounting structure.
  8. Kawahara Toshimi,JPX ; Suwa Mamoru,JPX ; Onodera Masanori,JPX ; Monma Syuichi,JPX ; Nakaseko Shinya,JPX ; Hozumi Takashi,JPX ; Yoneda Yoshiyuki,JPX ; Nomoto Ryuji,JPX, Semiconductor device and mounting structure.
  9. Yoneda, Yoshiyuki; Nomoto, Ryuji; Motooka, Toshiyuki; Tsuji, Kazuto; Kasai, Junichi; Kawahara, Toshimi; Sakoda, Hideharu; Itasaka, Kenji; Kamifukumoto, Terumi, Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame.
  10. Yoshiyuki Yoneda JP; Ryuji Nomoto JP; Toshiyuki Motooka JP; Kazuto Tsuji JP; Junichi Kasai JP; Toshimi Kawahara JP; Hideharu Sakoda JP; Kenji Itasaka JP; Terumi Kamifukumoto JP, Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame.
  11. Takagi Shinichi,JPX ; Suzuki Akinobu,JPX, Semiconductor element module and semiconductor device which prevents short circuiting.
  12. Maniscalco Joseph Francis ; McLaughlin Karen Patricia ; Semkow Krystyna Waleria, Semiconductor package having etched-back silver-copper braze.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로