초록 ▼

A data processing system is described utilising multiple instruction sets. The program instruction words are supplied to a processor core 2 via an instruction pipeline 6. As program instruction words of a second instruction set pass along the instruction pipeline, they are mapped to program instruct

A data processing system is described utilising multiple instruction sets. The program instruction words are supplied to a processor core 2 via an instruction pipeline 6. As program instruction words of a second instruction set pass along the instruction pipeline, they are mapped to program instruction words of the first instruction set. The second instruction set has program instruction words of a smaller bit size than those of the first instruction set and is a subset of the first instruction set. Smaller bit size improves code density, whilst the nature of the second instruction set as a subset of the first instruction set enables a one-to-one mapping to be efficiently performed and so avoid the need for a dedicated instruction decoder for the second instruction set.

대표청구항 ▼

Apparatus for processing data, said apparatus comprising: (i) a processor core responsive to a plurality of core control signals; (ii) decoding means for decoding P bits of an X-bit program instruction word of a first instruction set to generate said core control signals; (iii) an instruction pipeli

Apparatus for processing data, said apparatus comprising: (i) a processor core responsive to a plurality of core control signals; (ii) decoding means for decoding P bits of an X-bit program instruction word of a first instruction set to generate said core control signals; (iii) an instruction pipeline through which instruction program words are passed to said decoding means; and (iv) first mapping means responsive to a Y-bit program instruction word of a second instruction set passing along said instruction pipeline for mapping Q bits of said Y-bit program instruction word to said P bits of a corresponding X-bit program instruction word for decoding by said decoding means, wherein (v) Y is less than X, P is less than X and said second instruction set is a subset of said first instruction set; and (vi) instruction program words pass through said instruction pipeline over a plurality of processing cycles, one of said processing cycles being a decode cycle, said decoding means being operative to produce said core control signals by the end of said decode cycle and said first mapping means being operative to produce said P bits of said corresponding X-bit program instruction word during a first portion of said decode cycle to enable said decoding means still to produce said core control signals by the end of said decode cycle.