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Interconnect structures for integrated circuits

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0295957 (1994-08-25)
발명자 / 주소
  • Chung Henry W. (Cupertino CA)
출원인 / 주소
  • National Semiconductor Corporation (Santa Clara CA 02)
인용정보 피인용 횟수 : 26  인용 특허 : 0

초록

A multilevel interconnect structure which has a first horizontal metallic conductor disposed on the top of a previously formed first contact/via dielectric where the contact/via dielectric contains a contact/via hole. A horizontal interconnect is deposited over the first contact/via dielectric and h

대표청구항

A process for forming a metallic interconnect structure in an integrated circuit, comprising the steps of: forming a dielectric layer; forming a sacrificial layer on the dielectric layer; forming a mask having an opening to the sacrificial layer; etching the sacrificial layer through the mask to for

이 특허를 인용한 특허 (26)

  1. Paul R. Besser ; Errol Todd Ryan ; Frederick N. Hause ; Frank Mauersberger ; William S. Brennan ; John A. Iacoponi ; Peter J. Beckage, Contact each methodology and integration scheme.
  2. Nguyen Thien T. ; Gardner Mark I. ; May Charles E., Device and method for etching nitride spacers formed upon an integrated circuit gate conductor.
  3. Nguyen Thien T. ; Gardner Mark I. ; May Charles E., Device and method for etching spacers formed upon an integrated circuit gate conductor.
  4. Rodgers T. J. ; Geha Sam ; Petti Chris ; Yen Ting-Pwu, Edge metal for interconnect layers.
  5. Kinpara Shigeru,JPX ; Hanaoka Katsunari,JPX ; Kawashima Ikue,JPX ; Ito Kazunori,JPX, Fabrication process of a semiconductor device having an interconnection structure.
  6. Harvey Ian, Integrated circuit device interconnection techniques.
  7. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Integrated circuit having conductors of enhanced cross-sectional area.
  8. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Integrated circuit having conductors of enhanced cross-sectional area.
  9. Ardeshir J. Sidhwa ; Stephen John Melosky, Interconnect method and structure for semiconductor devices.
  10. Harvey Ian Robert ; Gabriel Calvin Todd, Method for achieving accurate SOG etchback selectivity.
  11. Shin Heon-jong,KRX, Method for forming side contact in a semiconductor device.
  12. Taguwa Tetsuya,JPX ; Yamada Yoshiaki,JPX, Method of fabricating semiconductor device.
  13. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Brennan William S. ; Hause Fred N. ; Dawson Robert ; Michael Mark W., Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer.
  14. Kim Jeong-Seok,KRX ; Park Joo-Wook,KRX, Methods of forming contacts for integrated circuits using chemical vapor deposition and physical vapor deposition.
  15. Ping-Chuan Wang ; Ronald G. Filippi ; Robert D. Edwards ; Edward W. Kiewra ; Roy C. Iggulden, Process of enclosing via for improved reliability in dual damascene interconnects.
  16. Harada,Yusuke, Semiconductor device.
  17. Harada,Yusuke, Semiconductor device.
  18. Hirotada Kuriyama JP; Kazuhito Tsutsumi JP, Semiconductor device.
  19. Kasai Naoki,JPX, Semiconductor device capable of easily filling contact conductor plug in contact hole.
  20. Harada, Yusuke, Semiconductor device having damascene interconnection structure that prevents void formation between interconnections.
  21. Harada, Yusuke, Semiconductor device having damascene interconnection structure that prevents void formation between interconnections.
  22. Yusuke Harada JP, Semiconductor device having damascene interconnection structure that prevents void formation between interconnections.
  23. Harada, Yusuke, Semiconductor device having damascene interconnection structure that prevents void formation between interconnections having transparent dielectric substrate.
  24. Drynan John Mark,JPX ; Koyama Kuniaki,JPX, Semiconductor device having ring-shaped conductive spacer which connects wiring layers.
  25. Kim, Kyoung-Hee; Choi, Gil-Heyun; Han, Kyu-Hee; Park, Byung-Lyul; Kim, Byung-Hee; Ahn, Sang-Hoon; Moon, Kwang-Jin, Semiconductor devices and methods of manufacturing semiconductor devices.
  26. Drynan John Mark,JPX ; Koyama Kuniaki,JPX, Structure of a contact hole in a semiconductor device and method of manufacturing the same.
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