초록 ▼

The present invention discloses an inductive circuit. The inductive circuit is fabricated on a semiconductor chip including a substrate layer and a dielectric layer. The inductive circuit includes an inductive core composed of high magnetic susceptible material (HMSM) surrounded by an dielectric lay

The present invention discloses an inductive circuit. The inductive circuit is fabricated on a semiconductor chip including a substrate layer and a dielectric layer. The inductive circuit includes an inductive core composed of high magnetic susceptible material (HMSM) surrounded by an dielectric layer. The dielectric layer which surrounds the inductive core is further surrounded by a conductive line which includes the bottom conductive lines the conductive lines in the ‘vias’through the surrounding dielectric layer and the top conductive lines. The conductive lines are patterned by employing IC fabrication processes. Thus the inductive core, the dielectric layer surrounding the inductive core, and the surrounding conductive line form an inductive circuit and the inductive circuit is formed on the semi-conductor chip which includes the substrate a layer and a dieletric layer.

대표청구항 ▼

An integrated-circuit (IC) device includes a plurality of IC circuits integrated on a semiconductor chip, said device comprising: an inductive circuit including an inductive line formed by connecting a plurality of conductive lines disposed on several layers in said semiconductor chip by utilizing a

An integrated-circuit (IC) device includes a plurality of IC circuits integrated on a semiconductor chip, said device comprising: an inductive circuit including an inductive line formed by connecting a plurality of conductive lines disposed on several layers in said semiconductor chip by utilizing a plurality of lithographically-formed via-connecting lines penetrating between said several layers in said semiconductor chip thus forming an IC inductive coil in said semiconductor chip; and said inductive line disposed on several layers and said plurality of via-connecting lines are fabricated by lithographic processes on said semiconductor chip wherein said line-widths between said inductive lines and said via-connecting lines being substantially in a submicron range whereby said IC inductive circuit are integratable with said plurality of IC circuits of said IC device in a very large scale integrated (VLSI) circuit and ultra large scale integrated (ULSI) circuit.