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Capacitor with buried isolated electrode

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01G-004/005
출원번호 US-0415499 (1995-04-03)
발명자 / 주소
  • Monsorno Richard (Jacksonville FL)
출원인 / 주소
  • American Technical Ceramics Corporation (Huntington Station NY 02)
인용정보 피인용 횟수 : 35  인용 특허 : 5

초록

A capacitor includes a planar electrode layer which is mounted between a pair of dielectric layers. The electrode layer generally is centered inwardly with respect to the dielectric layers leaving an outward margin of dielectric material. One of the dielectric layers has two spaced apart contact mem

대표청구항

A buried layer capacitor comprising: a first dielectric layer, with said first dielectric layer having a length dimension and a width dimension, and with said first dielectric layer having a first surface and a second surface; an electrode layer, with said electrode layer having a length dimension a

이 특허에 인용된 특허 (5)

  1. Nishimura Tsutomu (Uji JPX) Nakatani Seiichi (Hirakata JPX) Yuhaku Satoru (Osaka JPX) Hakotani Yasuhiko (Nishinomiya JPX) Kikuchi Tatsuro (Hirakata JPX), Laminated ceramic capacitor.
  2. Mori Yoshiaki (Nagaokakyo JPX) Takagi Hiroshi (Nagaokakyo JPX) Sakabe Yukio (Nagaokakyo JPX), Monolithic ceramic capacitor.
  3. Coleman James H. (Wichita Falls TX), Monolithic ceramic capacitor with fuse link.
  4. Takeda Takeshi (Kawasaki JPX) Tsuchiya Sohji (Kanagawa JPX) Watanabe Yoshio (Yokohama JPX) Sekido Satoshi (Kawasaki JPX), Multi-layered dielectric element.
  5. Yamada Kenichi (Nagaokakyo JPX) Tachi Kunio (Nagaokakyo JPX), Multilayer capacitor.

이 특허를 인용한 특허 (35)

  1. Devoe, Daniel; Devoe, Alan; Devoe, Lambert; Trinh, Hung, CERAMIC CHIP CAPACITOR OF CONVENTIONAL VOLUME AND EXTERNAL FORM HAVING INCREASED CAPACITANCE FROM USE OF CLOSELY SPACED INTERIOR CONDUCTIVE PLANES RELIABLY CONNECTING TO POSITIONALLY TOLERANT EXTERIO.
  2. Devoe, Daniel; Devoe, Alan; Devoe, Lambert; Trinh, Hung, CERAMIC CHIP CAPACITOR OF CONVENTIONAL VOLUME AND EXTERNAL FORM HAVING INCREASED CAPACITANCE FROM USE OF CLOSELY SPACED INTERIOR CONDUCTIVE PLANES RELIABLY CONNECTING TO POSITIONALLY TOLERANT EXTERIO.
  3. Devoe, Daniel; Devoe, Alan; Devoe, Lambert; Trinh, Hung, CERAMIC CHIP CAPACITOR OF CONVENTIONAL VOLUME AND EXTERNAL FORM HAVING INCREASED CAPACITANCE FROM USE OF CLOSELY SPACED INTERIOR CONDUCTIVE PLANES RELIABLY CONNECTING TO POSITIONALLY TOLERANT EXTERIO.
  4. Daniel Devoe ; Alan D. Devoe ; Lambert Devoe, CERAMIC CHIP CAPACITOR OF CONVENTIONAL VOLUME AND EXTERNAL FORM HAVING INCREASED CAPACITANCE FROM USE OF CLOSELY-SPACED INTERIOR CONDUCTIVE PLANES RELIABLY CONNECTING TO POSITIONALLY-TOLERANT EXTERIO.
  5. Link, Andreas; Metzger, Thomas; Schmidhammer, Edgar, Capacitor having an improved linear behavior.
  6. Monsorno,Richard V., Capacitor with buried electrode.
  7. Galvagni, John L.; Heistand, II, Robert; Korony, Georghe, Cascade capacitor.
  8. Devoe,Lambert; Devoe,Alan; Devoe,Daniel, Combined multilayer and single-layer capacitor for wirebonding.
  9. Fan,Chen Lu; Yang,Chieh; Chen,Li Ping, Computer enclosure with locking apparatus.
  10. Nobushige Moriwaki JP; Kazuhiro Yoshida JP; Kenichi Watanabe JP; Akio Shobu JP; Osamu Yamaoka JP; Yukio Tanaka JP, Electronic component.
  11. Mruz, John, Electronic component and method of making.
  12. Devoe, Daniel; Devoe, Alan; Devoe, Lambert, Integrated broadband ceramic capacitor array.
  13. Devoe, Daniel; Devoe, Alan; Devoe, Lambert, Integrated broadband ceramic capacitor array.
  14. Devoe, Daniel; Devoe, Alan; Devoe, Lambert, Integrated broadband ceramic capacitor array.
  15. Devoe,Daniel; Devoe,Alan; Devoe,Lambert, Integrated broadband ceramic capacitor array.
  16. Devoe,Daniel; Devoe,Alan; Devoe,Lambert, Integrated broadband ceramic capacitor array.
  17. Purple, Robert; Young, Marilynn; Eisenberger, Larry, Integrated capacitor assembly.
  18. Purple,Robert; Young,Marilynn; Eisenberger,Larry, Integrated capacitor assembly.
  19. Robert A. Stevenson, Low inductance four terminal capacitor lead frame.
  20. Heistand, II,Robert; Galvagni,John L.; Korony,Georghe, Method for adjusting performance characteristics of a multilayer component.
  21. Devoe, Alan; Devoe, Lambert; Trinh, Hung, Method of making an essentially monolithic capacitor.
  22. Devoe,Alan; Devoe,Lambert; Trinh,Hung, Method of making an essentially monolithic capacitor.
  23. Mruz,John, Method of making an orientation-insensitive ultra-wideband coupling capacitor.
  24. Devoe, Alan; Devoe, Lambert; Trinh, Hung, Method of making single layer capacitor.
  25. Ritter, Andrew P.; Berolini, Marianne, Multi-layer electronic device.
  26. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  27. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  28. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  29. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  30. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  31. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device comprising a pixel unit including an auxiliary capacitor.
  32. Devoe, Alan; Devoe, Lambert; Trinh, Hung, Single layer capacitor.
  33. Devoe, Alan; Devoe, Lambert; Trinh, Hung, Single layer capacitor.
  34. Devoe, Alan; Devoe, Lambert; Trinh, Hung, Single layer capacitor.
  35. Devoe, Daniel F.; Devoe, Lambert; Devoe, Alan D., Single layer capacitor with dissimilar metallizations.
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