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Method for forming inlaid interconnects in a semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0444184 (1995-05-18)
발명자 / 주소
  • Fiordalice Robert W. (Austin TX) Maniar Papu D. (Austin TX) Klein Jeffrey L. (Austin TX)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 155  인용 특허 : 13

초록

In the present invention, an inlaid interconnect (44) is formed by chemical mechanical polishing. A polish assisting layer (31), in the form of an aluminum nitride layer, is formed between an interlayer dielectric (30) and an interconnect metal (42) to prevent dishing or cusping of the interconnect

대표청구항

A method for forming a semiconductor device comprising the steps of: providing a semiconductor substrate; depositing a dielectric layer over the semiconductor substrate; depositing a polish assisting layer on the dielectric layer, wherein the polish assisting layer is comprised of aluminum nitride;

이 특허에 인용된 특허 (13)

  1. Keller Stephen A. (Sugar Land TX) Spry Piper A. (Sugar Land TX) Adams Martha S. (Rosenberg TX) Harper Ralph G. (Guy TX), Aluminum contact etch mask and etchstop for tungsten etchback.
  2. Sune Ching-Tzong (Hsinchu TWX) Lu Chih-Yuan (Hsinchu TWX), Chemical/mechanical polishing for ULSI planarization.
  3. Dixit Pankaj (Sunnyvale CA) Sliwa Jack (Los Altos Hills CA) Klein Richard K. (Mountain View CA) Sander Craig S. (Mountain View CA) Farnaam Mohammad (Santa Clara CA), Contact plug and interconnect employing a barrier lining and a backfilled conductor material.
  4. Poon Stephen S. (Austin TX), Method for fabricating a semiconductor device having a planar surface.
  5. Roth Scott S. (Austin TX) Ray Wayne J. (Austin TX) Kirsch Howard C. (Austin TX), Method for planarizing a layer of material.
  6. Poon Stephen S. (Austin TX) Gelatos Avgerinos V. (Austin TX), Method for polish planarizing a semiconductor substrate by using a boron nitride polish stop.
  7. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  8. Doan Trung T. (Boise ID) De Bruin Leendert (Eindhoven NLX) Grief Malcolm K. (Eindhoven NLX) Godon Harald (Tornesch DEX), Method of forming a configuration of interconnections on a semiconductor device having a high integration density.
  9. Chang Kenneth (Hopewell Junction NY) Cosman David C. (Newburgh NY) Gartner Helmut M. (Wappingers Falls NY) Hoeg ; Jr. Anthony J. (Wappingers Falls NY), Method of forming thin film interconnection systems.
  10. Savkar Sunil W. (Austin TX) Travis Edward O. (Austin TX), Method of making a semiconductor device having an improved metallization structure.
  11. Mutsaers Cornelis A.H.A. (Eindhoven NLX) Wolters Robertus A.M. (Eindhoven NLX), Method of manufacturing a semiconductor device in which a surface of a semiconductor body is provided with mutually-insu.
  12. Huttemann Robert D. (Macungie PA) Tsai Nun-Sian (Allentown PA), Semiconductor device having tungsten plugs.
  13. Cochran William T. (New Tripoli PA) Garcia Agustin M. (Allentown PA) Hills Graham W. (Allentown PA) Yeh Jenn L. (Macungie PA), Semiconductor devices having multi-level metal interconnects.

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