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NTIS 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0270650 (1994-07-05) |
우선권정보 | JP-0163706 (1993-07-02) |
발명자 / 주소 |
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출원인 / 주소 |
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인용정보 | 피인용 횟수 : 7 인용 특허 : 0 |
A pipelined data processing arrangement which is subject to an instruction interrupt is disclosed. The pipelined arrangement is provided with a plurality of stages each of which has a temporary storage. In order to increase an actual time for executing instructions in the pipelined arrangement, the
A pipelined data processing arrangement having a plurality of stages which are coupled in series and each of which includes temporary storage means, comprising: a first stage for successively issuing a plurality of instructions in synchronism with time slots, said first stage including storage means
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