[특허]Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multi

Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multi 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-012/08 G06F-013/00
출원번호	US-0414763 (1995-03-31)
발명자 / 주소	Nishtala Satyanarayana (Cupertino CA) Ebrahim Zahir (Mountain View CA) Van Loo William C. (Palo Alto CA) Loewenstein Paul (Palo Alto CA) Lee Sue K. (San Mateo CA) Coffin III Louis F. (San Jose CA)
출원인 / 주소	Sun Microsystems, Inc. (Mountain View CA 02)
인용정보	피인용 횟수 : 85 인용 특허 : 0

초록 ▼

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor. Each data processor has a writeback buffer for storing the data block previously stored in a victimized cache line until its respective writeback transaction is completed and an Nth+1 Dtag for storing the cache state of a cache line associated with a read transaction which is executed prior to an associated writeback transaction of a read-writeback transaction pair. Accordingly, upon a cache miss, the interconnect may execute the read and writeback transactions in parallel relying on the writeback buffer or Nth+1 Dtag to accommodate any ordering of the transactions.

대표청구항 ▼

A computer system, comprising: a system controller; a main memory coupled to said system controller; a data processor having a cache memory having N cache lines for storing N data blocks, where N is an integer greater than 4, N master cache tags (Etags), including one Etag for each said cache line in said cache memory, and a writeback buffer for storing a dirty victim data block displaced from said cache memory until it is written back into said main memory; said Etag for each cache line storing an address index and an Etag state value that indicates whether said data block stored in said cache line includes data modified by said data processor; said data processor including a master interface, coupled to said system controller, for sending memory transaction requests to said system controller, said memory transaction requests including read requests and writeback requests; each memory transaction request specifying an address for an associated data block to be read or written; said master interface further including cache coherence logic for responding to a cache miss on any cache line in said cache memory by (A) generating a read request, and (B) when said cache miss requires a cache line to be victimized and said victim cache line includes modified data, according to the Etag state value in the corresponding Etag, storing the data block having said modified data in said writeback buffer and generating a writeback request; said system controller including a set of N duplicate cache tags (Dtags), each Dtag corresponding to one of said Etags and storing a Dtag state value and the same address index as the corresponding Etag; said Dtag state value indicating whether said data block stored in the corresponding cache line includes data modified by said data processor; said system controller further including an N+1th Dtag; said system controller including memory transaction request logic for processing each said memory transaction request by said data processor; said system controller\s memory transaction request logic including writeback logic for processing said writeback request by writing the data block in said writeback buffer into said main memory and invalidating the state value in the corresponding Dtag; said system controller\s memory transaction request logic including read logic for processing said read request by (A) identifying a victim cache line, if any, in said cache memory and accessing the Dtag corresponding to said victim cache line to determine whether processing said read request will displace from said cache memory a data block that includes modified data, (B) retrieving a data block from said main memory corresponding to said read request and providing it to said data processor for storage in said data processor\s cache memory, (C) storing a Dtag state value and address tag in the Dtag corresponding to said victim cache line when processing said read request does not displace from said cache memory a modified data block and when said corresponding Dtag\s state value is invalid, (D) storing said Dtag state value and address tag for said read request in said N+1th Dtag when processing said read request does displace from said cache memory a modified data block and said corresponding Dtag\s state value is not invalid, and (E) transferring said N+1th Dtag into said Dtag corresponding to said victim cache line when said writeback logic invalidates said Dtag state value in said corresponding Dtag; and wherein said memory transaction request logic processes said read request and writeback request such that processing of either of said read request and writeback request may be completed prior to the other in accordance with resource availability for processing said requests.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
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연합인증

Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multi 원문보기

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Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multi 원문보기

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