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Baseboard and daughtercard apparatus for reconfigurable computing systems 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01R-023/68
  • H05K-001/11
출원번호 US-0348280 (1994-11-30)
발명자 / 주소
  • Tredennick Harry L. (Los Gatos CA) Van den Bout David E. (Apex NC)
출원인 / 주소
  • Altera Corporation (San Jose CA 02)
인용정보 피인용 횟수 : 69  인용 특허 : 0

초록

A reconfigurable apparatus for computing systems including a set of baseboards and a family of daughtercards, together with a programmable interface to an external bus for a host system. Daughtercards attach to the baseboard through complementary connectors mounted on the baseboard and the daughterc

대표청구항

A daughtercard for use in a reconfigurable baseboard/daughtercard apparatus, comprising: a first array of electrical connectors disposed at a first edge, and on a top side of said daughtercard; a second array of electrical connectors identical to said first array of electrical connectors disposed at

이 특허를 인용한 특허 (69)

  1. Franz, John P.; Little, Jr., Walton S.; Pham, Tuan A.; Nguyen, John D., Adaptable plug-in mezzanine card for blade servers.
  2. Stahl,Douglas Lee; Formisano,David R.; Saffarian,Andy; Khoury,Marwan, Advanced mezzanine card adapter.
  3. Nguyen, John D.; Kolas, Jon, Apparatus for inexpensive mezzanine-type card board-to-board connector blind mate alignment system using printed circuit board material.
  4. Gierut Lawrence, Circuit board assembly.
  5. Kida Luis S. ; Crutchfield Perry W. ; Dickey Kenneth W. ; Musfeldt Curtis D. ; Vachon Robert J. G. ; Wilson Wayne G., Circuit card assembly footprint providing reworkable interconnection paths for use with a surface mount device.
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  7. Schroeder, Charles G.; Graf, Christopher F.; Nishiguchi, Ciro T.; D'Souza, Nigel G.; Baker, Daniel J.; Magruder, Thomas D., Customizing operation of a test instrument based on information from a system under test.
  8. Andrade,Hugo A.; Odom,Brian Keith; Butler,Cary Paul; Peck,Joseph E.; Petersen,Newton G., Debugging a program intended to execute on a reconfigurable device using a test feed-through configuration.
  9. Beal Samuel W. ; Kaptonoglu Sinan ; Lien Jung-Cheun ; Shu William ; Chan King W. ; Plants William C., Enhanced field programmable gate array.
  10. McGowan John E., Field programmable gate array with mask programmed analog function circuits.
  11. John E. McGowan, Field programmable gate array with mask programmed input and output buffers.
  12. McGowan John E., Field programmable gate array with mask programmed input and output buffers.
  13. von Kaenel, Vincent R., Flexible packaging for chip-on-chip and package-on-package technologies.
  14. von Kaenel, Vincent R., Flexible packaging for chip-on-chip and package-on-package technologies.
  15. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Generating a hardware description of a block diagram model for implementation on programmable hardware.
  16. Kodosky,Jeffrey L.; Andrade,Hugo; Odom,Brian K.; Butler,Cary P., Graphical program having a timing specification and method for conversion into a hardware implementation.
  17. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Graphical program with various function icons and method for conversion into hardware implementation.
  18. Dye, Robert E.; Shah, Darshan; Rogers, Steve; Richardson, Greg; Luick, Dean A., Graphical programming system with block diagram execution and distributed user interface display.
  19. Dye, Robert E.; Shah, Darshan; Rogers, Steve; Richardson, Greg; Luick, Dean A., Graphical programming system with distributed block diagram execution and front panel display.
  20. Jasper Jonathan C., High speed stackable memory system and device.
  21. Bhakta Jayesh R. ; Vakilian Kavous, High-density computer module with stacked parallel-plane packaging.
  22. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Implementing a data flow block diagram having a control flow node on a programmable hardware element.
  23. Kodosky,Jeffrey L.; Andrade,Hugo; Odom,Brian K.; Butler,Cary P., Implementing a model on programmable hardware.
  24. Heile Francis B. ; Fairbanks Brent A., Incremental compilation of electronic design for work group.
  25. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
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  27. Goffinet Kevin Patrick ; Rafferty ; Jr. Francis Darrell ; Songer Gail Marie ; Webb James Francis ; Wedinger Jeffrey Keith ; Young Lloyd Phillip, Method and apparatus for configuring the physical setup of multiple printers on a network.
  28. Daniel, Jurgen H.; Ng, Tse Hga, Method for event sensing employing a printed event sensor.
  29. Brunelle, Steven J.; Momenpour, Saeed, Methods of testing memory devices.
  30. Brunelle, Steven J.; Momenpour, Saeed, Motherboard memory slot ribbon cable and apparatus.
  31. Brunelle,Steven J.; Momenpour,Saeed, Motherboard memory slot ribbon cable and apparatus.
  32. Kassas, Zaher; Lewis, James M., Multi-channel algorithm infrastructure for programmable hardware elements.
  33. Darwish,Mohammad; Pucker,Leonard G.; Smith,Phillip D.; Woo,Roy Gee Leong, Multiple configurable I/O common mezzanine cards.
  34. Forinash,John M.; Bigot,Peter A.; Jensen,John D.; Spivey,Gary E., Negotiating electrical signal pathway compatibility between reconfigurable circuit modules.
  35. Portman Roland F. ; Gregorios Edgar Jhay, Printed circuit board assembly.
  36. Tohru Ohtaki JP; Tohru Ohsaka JP, Printed wiring board unit for use with electronic apparatus.
  37. Vogel, Ernest P.; Nicolino, Jr., Sam J.; Hasslen, III, Robert J.; Martinez, Fernando G., Prototype development system and method.
  38. Forinash, John M.; Bigot, Peter A.; Jensen, John D.; Spivey, Gary E., Reconfigurable circuit modules.
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  48. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Specifying and targeting portions of a graphical program for execution by multiple targets.
  49. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Specifying and targeting portions of a graphical program for real-time response.
  50. Kodosky,Jeffrey L.; Andrade,Hugo; Odom,Brian K.; Butler,Cary P., Specifying portions of a graphical program for respective execution by a processor and a programmable hardware element.
  51. Farzad Khosrowpour ; Victor Key Pecone, Stacked I/O bridge circuit assemblies having flexibly configurable connections.
  52. Gary S. Costner, System and method for cartridge-based, geometry-variant scalable electronic systems.
  53. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., System and method for configuring a device to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
  54. Chandhoke, Sundeep; Vazquez, Nicolas; Schultz, Kevin L., System and method for configuring a hardware device to execute a prototype.
  55. Peck,Joseph E.; Novacek,Matthew; Andrade,Hugo A.; Petersen,Newton G., System and method for configuring a reconfigurable system.
  56. Kodosky Jeffrey L. ; Andrade Hugo ; Odom Brian K. ; Butler Cary P., System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
  57. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian Keith; Butler, Cary Paul; Schultz, Kevin L., System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
  58. Kodosky,Jeffrey L.; Andrade,Hugo; Odom,Brian K.; Butler,Cary P., System and method for converting a graphical program including a structure node into a hardware implementation.
  59. Schultz, Kevin L.; Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian Keith; Butler, Cary Paul, System and method for deploying a graphical program on an image acquisition device.
  60. Dunn, Jr., Richard Anthony, System and methods for scalable parallel data processing and process control.
  61. Dunn, Jr., Richard Anthony, Systems and methods for scalable parallel data processing and process control.
  62. Ilic, Kosta; Blasig, Dustyn K., Testing a graphical program intended for a programmable hardware element.
  63. Leedy, Glenn J, Three dimension structure memory.
  64. Leedy, Glenn J, Three dimensional memory structure.
  65. Leedy, Glenn J, Three dimensional memory structure.
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  67. Leedy, Glenn J, Three dimensional structure memory.
  68. Conder Alan D., Vacuum compatible miniature CCD camera head.
  69. Leedy,Glenn J., Vertical system integration.
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