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Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/28
  • H01L-021/308
  • H01L-021/66
출원번호 US-0406637 (1995-03-20)
발명자 / 주소
  • Wood Alan G. (Boise ID) Doan Trung T. (Boise ID) Farnworth Warren M. (Nampa ID) Corbett Tim J. (Boise ID)
출원인 / 주소
  • Micron Technology, Inc. (Boise ID 02)
인용정보 피인용 횟수 : 46  인용 특허 : 25

초록

A process for forming die contacting substrate for establishing ohmic contact with the die is formed with raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact membe

대표청구항

A method for forming a contact member for establishing electrical contact with a contact location on a discrete, unpackaged semiconductor die, said contact location formed as a metal pad, said method comprising: forming a substrate; forming a raised contact on the substrate for contacting the contac

이 특허에 인용된 특허 (25)

  1. Svendsen Leo G. (Swindon GB2) Bates Nigel R. (Swindon GB2), Anisotropically electrically conductive article.
  2. Hoeberechts Arthur M. E. (Eindhoven NLX) Peters Petrus J. M. (Eindhoven NLX), Combination of a support and a semiconductor body and method of manufacturing such a combination.
  3. Swart Mark A. (Upland CA), Electrical test probe contact tip.
  4. Bean Kenneth E. (Richardson TX) Lloyd William W. (Richardson TX), FET and bipolar device and circuit process with maximum junction control.
  5. Malhi Satwinder (Garland TX) Kwon Oh K. (Richardson TX) Mahant-Shetti Shivaling S. (Richardson TX), Flip-chip test socket adaptor and method.
  6. Kwon Oh-Kyong (Plano TX) Hashimoto Masashi (Garland TX) Malhi Satwinder (Garland TX) Born Eng C. (Richardson TX), Full wafer integrated circuit testing device.
  7. Robillard David R. (Westboro MA) Michaels Robert L. (Marlboro MA), Integrated test and assembly device.
  8. Robillard David R. (Westboro MA) Michals Robert L. (Marlboro MA), Integrated test and assembly device.
  9. Leedy Glenn (1061 E. Mountain Dr. Santa Barbara CA 93108), Interconnection structure for integrated circuits and method for making same.
  10. Littlebury Hugh W. (Chandler AZ) Simmons Marion I. (Tempe AZ), Low resistance probe for semiconductor.
  11. Leedy Glenn J. (1061 E. Mountain Dr. Santa Barbara CA 93108), Making and testing an integrated circuit using high density probe points.
  12. Elder Richard A. (Dallas TX) Wilson Arthur M. (Dallas TX) Bagen Susan V. (Dallas TX) Miller Juanita G. (Richardson TX), Method for fabrication of probe card for testing of semiconductor devices.
  13. Farnworth Warren M. (Nampa ID) Grief Malcolm (Boise ID) Sandhu Gurtej S. (Boise ID), Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor cir.
  14. Lehman-Lamer Gail R. (Hillsboro OR), Method of fabricating a contact device.
  15. Malhi Satwinder (Garland TX) Kwon Oh-Kyong (Richardson TX), Method of forming an apparatus for burn in testing of integrated circuit chip.
  16. Leedy Glenn J. (1061 E. Mountain Dr. Santa Barbara CA 93108), Method of making and testing an integrated circuit.
  17. Okino Hironobu (Kawasaki JPX) Fujiwara Akio (Chigasaki JPX) Akiba Yutaka (Fujisawa JPX) Kasukabe Susumu (Yokohama JPX) Fujita Tsuyoshi (Yokohama JPX) Mitani Masao (Yokohama JPX) Hirota Kazuo (Chigasa, Method of manufacturing probing head for testing equipment of semi-conductor large scale integrated circuits.
  18. Kawade Hisaaki (Atsugi JPX) Kawada Haruki (Yokohama JPX) Sakai Kunihiro (Isehara JPX) Matsuda Hiroshi (Isehara JPX) Morikawa Yuko (Kawasaki JPX) Yanagisawa Yoshihiro (Atsugi JPX) Kaneko Tetsuya (Yoko, Microprobe preparation thereof and electronic device by use of said microprobe.
  19. Elder Richard A. (Dallas TX) Johnson Randy (Carrollton TX) Frew Dean L. (Garland TX) Wilson Arthur M. (Dallas TX), Non-destructive burn-in test socket for integrated circuit die.
  20. Liu Jui-Hsiang (Chandler AZ) Olsen Dennis R. (Scottsdale AZ), Probe card for testing unencapsulated semiconductor devices.
  21. Niwayama Kazuhiko (Itami JPX) Nakagawa Tsutomu (Itami JPX) Tokunoh Futoshi (Itami JPX) Yoshida Shigekazu (Itami JPX), Semiconductor device.
  22. Blonder Greg E. (Summit NJ) Fulton Theodore A. (Warren NJ), Semiconductor integrated circuit chip-to-chip interconnection scheme.
  23. Reid Lee R. (Plano TX) Cody Tommy D. (Garland TX), Solid state multiprobe testing apparatus.
  24. Lee James C. K. (Los Altos Hills CA) Amdahl Gene M. (Atherton CA) Beck Richard (Cupertino CA) Lee Chune (San Francisco CA) Hu Edward (Sunnyvale CA), System for detachably mounting semiconductors on conductor substrate.
  25. Barsotti Christina C. (Vancouver WA) Schamel Alfred H. (West Linn OR), Wafer probe with transparent loading member.

이 특허를 인용한 특허 (46)

  1. Kaviani, Alireza S.; Maidee, Pongstorn; Bolsens, Ivo, Active-by-active programmable device.
  2. Patel Sunil A. ; Chia Chok J. ; Desai Kishor V., Apparatus and method for improving ball joints in semiconductor packages.
  3. Moden, Walter L.; Ahmad, Syed S.; Chapman, Gregory M.; Jiang, Tongbi, Apparatus and method for modifying the configuration of an exposed surface of a viscous fluid.
  4. Moden,Walter L.; Ahmad,Syed S.; Chapman,Gregory M.; Jiang,Tongbi, Apparatus for modifying the configuration of an exposed surface of a viscous fluid.
  5. Farnworth,Warren M.; Grief,Malcolm; Sandhu,Gurtej S., Apparatuses configured to engage a conductive pad.
  6. Chang Chung-Tao,TWX ; Wang Chia-Chung,TWX ; Huang Hsin-Chien,TWX, Built-in stress pattern on IC dies and method of forming.
  7. Wark James M. ; Akram Salman, Carriers including projected contact structures for engaging bumped semiconductor devices.
  8. Frye Robert Charles ; Low Yee Leng ; O'Connor Kevin John, Chip-on-chip IC packages.
  9. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Compliant interconnect for testing a semiconductor die.
  10. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Compliant interconnect for testing a semiconductor die.
  11. Farnworth,Warren M.; Grief,Malcolm, Engagement Probes.
  12. Farnworth,Warren M.; Grief,Malcolm; Sandhu,Gurtej S., Engagement probe having a grouping of projecting apexes for engaging a conductive pad.
  13. Karp, James; Young, Steven P.; New, Bernard J.; Nance, Scott S.; Crotty, Patrick J., Hybrid integrated circuit device.
  14. Ahmad, Syed Sajid, Integrated circuit devices including connection components mechanically and electrically attached to semiconductor dice.
  15. Farnworth Warren M. ; Akram Salman, Interconnect for semiconductor components and method of fabrication.
  16. Farnworth Warren M. ; Akram Salman, Interconnect for semiconductor components and method of fabrication.
  17. Roger E. Weiss ; Everett F. Simons, Interconnection components with integral conductive elastomeric sheet material, and method of manufacturing same.
  18. Duesman Kevin ; Farnworth Warren M., Method and apparatus for aligning an optic fiber with an opto-electronic device.
  19. Walter L. Moden ; Syed S. Ahmad ; Gregory M. Chapman ; Tongbi Jiang, Method and apparatus for applying adhesives to a lead frame.
  20. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Method and apparatus for burning-in semiconductor devices in wafer form.
  21. Farnworth,Warren M.; Grief,Malcolm; Sandhu,Gurtej S., Method and apparatus for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability.
  22. Moden, Walter L.; Ahmad, Syed S.; Chapman, Gregory M.; Jiang, Tongbi, Method for applying adhesives to a lead frame.
  23. Ahmad, Syed Sajid, Method for controlling the depth of immersion of a semiconductor element in an exposed surface of a viscous fluid.
  24. Mori Yoshihisa (Ibaraki JPX) Hino Atsushi (Ibaraki JPX) Ishizaka Hitoshi (Ibaraki JPX), Method for fabrication of probe structure and circuit substrate therefor.
  25. Wark, James M.; Akram, Salman, Method for making projected contact structures for engaging bumped semiconductor devices.
  26. Slocum Alexander H., Method of manufacturing ball grid arrays for improved testability.
  27. Weiss, Roger E.; Simons, Everett F., Method of manufacturing interconnection components with integral conductive elastomeric sheet material.
  28. Downes ; Jr. Francis Joseph ; Fuerniss Stephen Joseph ; Hill Gary Ray ; Ingraham Anthony Paul ; Markovich Voya Rista ; Molla Jaynal Abedin, Method of planarizing a curved substrate and resulting structure.
  29. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of temporarily, then permanently, connecting to a semiconductor device.
  30. Liu Hermen,TWX ; Huang Yimin,TWX, Method of testing and packaging a semiconductor chip.
  31. Ahmad Syed Sajid, Methods for simultaneously electrically and mechanically attaching lead frames to semiconductor dice and the resulting elements.
  32. Wark,James M.; Akram,Salman, Methods of making projected contact structures for engaging bumped semiconductor devices.
  33. Akram Salman ; Hembree David R. ; Wood Alan G., Micromachined probe card having compliant contact members for testing semiconductor wafers.
  34. Akram Salman ; Hembree David R. ; Wood Alan G., Micromachined silicon probe card for semiconductor dice and method of fabrication.
  35. Eldridge,Benjamin N.; Grube,Gary W.; Khandros,Igor Y.; Mathieu,Gaetan L., Mounting spring elements on semiconductor devices, and wafer-level testing methodology.
  36. Akram Salman ; Farnworth Warren ; Wood Alan, Multi chip module having self limiting contact members.
  37. Akram Salman ; Farnworth Warren M., Non-oxidizing touch contact interconnect for semiconductor test systems and method of fabrication.
  38. Wood Alan G. ; Akram Salman ; Farnworth Warren M., Process for manufacturing a semiconductor package with bi-substrate die.
  39. Wark James M. ; Akram Salman, Projected contact structure for bumped semiconductor device and resulting articles and assemblies.
  40. Wark,James M.; Akram,Salman, Projected contact structures for engaging bumped semiconductor devices and methods of making the same.
  41. Wark,James M.; Akram,Salman, Projected contact structures for engaging bumped semiconductor devices and methods of making the same.
  42. Wood Alan G. ; Akram Salman ; Farnworth Warren M., Semiconductor package with bi-substrate die.
  43. Warren M. Farnworth ; Alan G. Wood ; Trung Tri Doan ; David R. Hembree, Semiconductor testing apparatus including substrate with contact members and conductive polymer interconnect.
  44. Kaviani, Alireza S.; Maidee, Pongstorn; Dellinger, Eric F., System-level interconnect ring for a programmable integrated circuit.
  45. Farnworth, Warren M.; Wood, Alan G.; Doan, Trung T.; Hembree, David R., Test apparatus for testing semiconductor dice including substrate with penetration limiting contacts for making electrical connections.
  46. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Wafer-level test and burn-in, and semiconductor process.
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