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Method of making flash memory cell 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/8247
출원번호 US-0938727 (1992-09-01)
발명자 / 주소
  • Chang Kuang-Yeh (Los Gatos CA) Nariani Subhash R. (San Jose CA) Boardman William J. (San Jose CA)
출원인 / 주소
  • VLSI Technology, Inc. (San Jose CA 02)
인용정보 피인용 횟수 : 52  인용 특허 : 18

초록

The present invention relates to a flash EEPROM cell using polysilicon-to-polysilicon hot electron emission to erase the memory contents of the cell. Exemplary embodiments include a side gate, a control gate, a floating gate and source and drain regions. Appropriate biasing of these gates and source

대표청구항

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequen

이 특허에 인용된 특허 (18)

  1. Wada Masashi (Yokohama JPX), Electrically erasable programmable read only memory.
  2. Wu Albert T. (Berkeley CA) Ko Ping K. (Hercules CA) Chan Tung-Yi (Berkeley CA) Hu Chenming (Hercules CA), Electrically programmable memory device employing source side injection.
  3. Arima Hideaki (Hyogo JPX) Okumura Yoshinori (Hyogo JPX) Genjo Hideki (Hyogo JPX) Ogoh Ikuo (Hyogo JPX) Yuzuriha Kohjiroh (Hyogo JPX) Nakashima Yuichi (Hyogo JPX), Electrically programmable non-volatile memory device and manufacturing method thereof.
  4. Gill Manzur (Rosharon TX) D\Arrigo Sebastiano (Houston TX) Lin Sung-Wei (Houston TX), Electrically-erasable, electrically-programmable read-only memory cell.
  5. Freiberger Philip E. (Santa Clara CA) Yau Leopoldo D. (Portland OR) Pan Cheng-Sheng (Sunnyvale CA) Sery George E. (San Franciso CA), Fabrication of interpoly dielctric for EPROM-related technologies.
  6. Wu Tsung-Ching (San Jose CA) Chern Geeng-Chuan (Cupertino CA), Fabrication process for programmable and erasable MOS memory device.
  7. Hsia Steve K. (Saratoga CA) Pang Chan-Sui (Sunnyvale CA) Chevallier Christopher J. (Sunnyvale CA), High density EEPROM cell and process for making the cell.
  8. Harari Eliyahou (2320 Friars La. Los Altos CA 94022), Highly compact EPROM and flash EEPROM devices.
  9. Kawakami Masumi (Miho JPX), Insulated-gate field-effect semiconductor device with doped regions in channel to raise breakdown voltage.
  10. Sugaya Tadashi (Nara JPX), Manufacturing method of semiconductor nonvolatile memory device.
  11. Sethi Rakesh B. (Campbell CA), Method of making a split floating gate EEPROM cell.
  12. Lee Roger R. (Boise ID) Lowrey Tyler A. (Boise ID) Gonzalez Fernando (Boise ID) Keller J. Dennis (Boise ID), Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transi.
  13. Matsutani Takeshi (Machida JPX), Method of producing insulated-gate field effect transistor.
  14. Fukatsu Shigemitsu (Okazaki JPX) Asai Akiyoshi (Nisshin JPX), Method of reducing the trap density of an oxide film for application to fabricating a nonvolatile memory cell.
  15. Lee Soo-Cheol (Seoul KRX), Nonvolatile semiconductor memory device and manufacturing method thereof.
  16. Itoh Hiroshi (Tokyo JPX), Process of fabricating field effect transistor with LDD structure.
  17. Lowrey Tyler A. (Boise ID) Chance Randal W. (Boise ID), Reduced mask manufacture of semiconductor memory devices.
  18. Gilgen Brent D. (Boise ID) Lowrey Tyler A. (Boise ID) Karniewicz Joseph J. (Boise ID) McQueen Anthony M. (Boise ID), Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynam.

이 특허를 인용한 특허 (52)

  1. Gang Bai ; Chunlin Liang, Complementary metal gates and a process for implementation.
  2. Park Jeong-Soo,KRX, Dual gate MOSFET fabrication method.
  3. Tuan, Hsing Ti; Leung, Chung Wai, Dummy structures that protect circuit elements during polishing.
  4. Tuan, Hsing Ti; Leung, Chung Wai, Dummy structures that protect circuit elements during polishing.
  5. Park Eun-Jeong,KRX, Flash memory cell and method of fabricating the same.
  6. Gambino, Jeffrey P.; Hsu, Louis L.; Mandelman, Jack A.; Wheeler, Donald C., Flash memory structure using sidewall floating gate.
  7. Gambino Jeffrey P. ; Hsu Louis L. ; Mandelman Jack A. ; Wheeler Donald C., Flash memory structure using sidewall floating gate and method for forming the same.
  8. Shimizu, Masahiro, High-speed rotating shaft of supercharger.
  9. Kaya Cetin, Integrated circuit having independently formed array and peripheral isolation dielectrics.
  10. Warren William L. ; Vanheusden Karel J. R. ; Fleetwood Daniel M. ; Devine Roderick A. B.,FRX ; Archer Leo B. ; Brown George A. ; Wallace Robert M., Memory device using movement of protons.
  11. Sung Kuo-Tung,TWX, Method (and device) for producing tunnel silicon oxynitride layer.
  12. Noro, Fumihiko; Ogura, Seiki, Method for fabricating the control and floating gate electrodes without having their upper surface silicided.
  13. Chi Min-hwa ; Teng Chih-sieh ; Bergemont Albert, Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells.
  14. Prinz Erwin J. ; Yeric Gregory M. ; Wu Kevin Yun-kang ; Chen Wei-Ming ; Baker Frank Kelsey, Method for forming an integrated circuit.
  15. Chang, Ching-Yu, Method for forming flash memory with high coupling ratio.
  16. Moriyama, Wakako; Kai, Naoki; Hazama, Hiroaki; Nagai, Keiki; Fukazawa, Yuji; Saki, Kazuo; Ozawa, Yoshio; Suizu, Yasumasa, Method for manufacturing semiconductor devices using thermal nitride films as gate insulating films.
  17. Bergemont Albert ; Chi Min-hwa, Method of fabricating a high density EEPROM cell.
  18. Chang Kuang-Yeh,TWX, Method of fabricating flash memory.
  19. Park Eun-Jeong,KRX, Method of fabricating flash memory cell.
  20. Nguyen Duc Bui, Method of forming a composite interpoly gate dielectric.
  21. Lam Chung H. ; Martin Dale W. ; Willets Christa R., Method of forming a point on a floating gate for electron injection.
  22. Van Houdt,Jan; Haspeslagh,Luc, Method of making a multibit non-volatile memory.
  23. Lim Min-Gyu,KRX, Method of making floating gate based memory device.
  24. Robin Lee TW, Method of manufacturing V-shaped flash memory.
  25. Sun Yu ; Chang Chi ; Ramsbey Mark T., Method of spacer formation and source protection after self-aligned source is formed and a device provided by such a met.
  26. Shimizu, Masahiro; Shibui, Yasuyuki, Motor driven supercharger with motor/generator cooling efficacy.
  27. Shibui, Yasuyuki; Shimizu, Masahiro, Motor-driven supercharger.
  28. Shibui, Yasuyuki; Shimizu, Masahiro, Motor-driven supercharger.
  29. Shimizu, Masahiro, Motor-driven supercharger.
  30. Shimizu, Masahiro; Shibui, Yasuyuki, Motor-driven supercharger.
  31. Van Houdt, Jan; Haspeslagh, Luc, Multibit non-volatile memory and method.
  32. Choi Woong Lim,KRX ; Ra Kyeong Man,KRX, Nonvolatile memory device.
  33. Hsing Ti Tuan ; Li-Chun Li ; Chung Wai Leung ; Thomas Tong-Long Chang, Nonvolatile memory structures and fabrication methods.
  34. Leung, Chung Wai; Hsiao, Chia-Shun; Chan, Vei-Han, Nonvolatile memory structures and fabrication methods.
  35. Leung, Chung Wai; Hsiao, Chia-Shun; Chan, Vei-Han, Nonvolatile memory structures and fabrication methods.
  36. Tuan, Hsing Ti; Li, Li-Chun, Nonvolatile memory structures and fabrication methods.
  37. Tuan, Hsing Ti; Li, Li-Chun, Nonvolatile memory structures and fabrication methods.
  38. Tuan, Hsing Ti; Li, Li-Chun; Chang, Thomas Tong-Long, Nonvolatile memory structures and fabrication methods.
  39. Kuo-Tung Sung TW, Poly spacer split gate cell with extremely small cell size.
  40. Sung Kuo-Tung,TWX, Poly spacer split gate cell with extremely small cell size.
  41. Cha Cher Liang,SGX ; Zhang Anqing,SGX ; Xie Zhifeng Joseph,SGX ; Chor Eng Fong,SGX, Production of reversed flash memory device.
  42. Shone,Fuja; Lee,I Long; Liu,Yi Ching; Chen,Hsin Chien; Chang,Wen Lin, Programming and manufacturing method for split gate memory cell.
  43. Noro, Fumihiko; Ogura, Seiki, Semiconductor memory and method for fabricating the same.
  44. Lim Min-Gyu,KRX, Semiconductor memory device and method for manufacturing the same.
  45. Ishige, Kiyokazu, Semiconductor memory device and method of fabricating the same.
  46. Sung Kuo-Tung,TWX, Split gate flash cell with extremely small cell size.
  47. Hsieh, Chia-Ta, Split gate flash with strong source side injection and method of fabrication thereof.
  48. Hung, Chih-Wei; Chen, Chih-Ming, Structure, fabrication and operation method of flash memory device.
  49. Shimizu, Masahiro; Takahashi, Yukio, Supercharger.
  50. Lam Chung Hon ; Miles Glen L. ; Nakos Jame Spiros ; Willets Christa R., Triple polysilicon embedded NVRAM cell and method thereof.
  51. Hsu, Louis L.; Lam, Chung H.; Mandelman, Jack A.; Radens, Carl J.; Tonti, William R., Twin-cell flash memory structure and method.
  52. Verhaar, Robertus Dominicus Joseph; Dormans, Guido Jozef Maria, Virtual-ground, split-gate flash memory cell arrangements and method for producing same.
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